Addc (Add Word Data Of Source Register And Carry Bit To Destination Register) - Fujitsu FR Family Instruction Manual

7.4 ADDC (Add Word Data of Source Register and Carry Bit to
Destination Register)
Adds the word data in "Rj" to the word data in "Ri" and carry bit, stores results to "Ri".

■ ADDC (Add Word Data of Source Register and Carry Bit to Destination Register)

Assembler format: ADDC Rj, Ri
Ri + Rj + C → Ri
Operation:
Flag change:
N :
Z :
V :
C :
Execution cycles: 1 cycle
Instruction format:
Example: ADDC R2, R3
N Z V C
C C C C
Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Set when the operation result is "0", cleared otherwise.
Set when an overflow has occurred as a result of the operation, cleared otherwise.
Set when a carry has occurred as a result of the operation, cleared otherwise.
MSB
1 0 1 0
Instruction bit pattern : 1010 0111 0010 0011
R2
1 2 3 4 5 6 7 8
R3
8 7 6 5 4 3 2 0
N Z V C
CCR
0 0 0 1
Before execution
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
0 1 1 1 Rj
LSB
Ri
R2
1 2 3 4 5 6 7 8
R3 9 9 9 9 9 9 9 9
N Z V C
CCR
1 0 0 0
After execution
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