Fujitsu FR Family Instruction Manual page 18

Page
"7.42 DIV3 (Correction when Remainder is 0)" is changed.
136
( "Instruction bit pattern : 1001 1111 0110 0000" is added. )
"7.43 DIV4S (Correction Answer for Signed Division)" is changed.
137
( "Instruction bit pattern : 1001 1111 0111 0000" is added. )
"7.44 LSL (Logical Shift to the Left Direction)" is changed.
138
( "Instruction bit pattern : 1011 0110 0010 0011" is added. )
"7.47 LSR (Logical Shift to the Right Direction)" is changed.
141
( "Instruction bit pattern : 1011 0010 0010 0011" is added. )
"7.50 ASR (Arithmetic Shift to the Right Direction)" is changed.
144
( "Instruction bit pattern : 1011 1010 0010 0011" is added. )
"7.53 LDI:32 (Load Immediate 32-bit Data to Destination Register)" is changed.
( "Instruction bit pattern : 1001 1111 1000 0011
147
"7.54 LDI:20 (Load Immediate 20-bit Data to Destination Register)" is changed.
148 ( "Instruction bit pattern : 1001 1011 0101 0011
"7.55 LDI:8 (Load Immediate 8-bit Data to Destination Register)" is changed.
149
( "Instruction bit pattern : 1100 0010 0001 0011" is added. )
"7.56 LD (Load Word Data in Memory to Register)"is changed.
150
( "Instruction bit pattern : 0000 0100 0010 0011" is added. )
"7.57 LD (Load Word Data in Memory to Register)" is changed.
151
( "Instruction bit pattern : 0000 0000 0010 0011" is added. )
"7.59 LD (Load Word Data in Memory to Register)" is changed.
153
( "o4" → "u4" )
"7.60 LD (Load Word Data in Memory to Register)" is changed.
154
( "Instruction bit pattern : 0000 0111 0000 0011" is added. )
"7.61 LD (Load Word Data in Memory to Register)" is changed.
156
( "Instruction bit pattern : 0000 0111 1000 0100" is added. )
"7.62 LD (Load Word Data in Memory to Program Status Register)" is changed.
157
Flag change: ( "Ri" → "R15")
"7.62 LD (Load Word Data in Memory to Program Status Register)" is changed.
158
( "Instruction bit pattern : 0000 0111 1001 0000" is added. )
"7.63 LDUH (Load Half-word Data in Memory to Register)" is changed.
159
( "Instruction bit pattern : 0000 0101 0010 0011" is added. )
"7.64 LDUH (Load Half-word Data in Memory to Register)" is changed.
160
( "Instruction bit pattern : 0000 0001 0010 0011" is added. )
"7.66 LDUB (Load Byte Data in Memory to Register)" is changed.
162
( "Instruction bit pattern : 0000 0110 0010 0011" is added. )
Changes (For details, refer to main body.)
: 1000 0111 0110 0101
: 0100 0011 0010 0001" is added. )
: 0100 0011 0010 0001" is added. )
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