Fujitsu FR Family Instruction Manual page 302

INDEX
Index
A
ADD
ADD (Add 4-bit Immediate Data to Destination
Register)............................................... 73
ADD (Add Word Data of Source Register to
Destination Register) ............................. 72
ADD2 (Add 4-bit Immediate Data to Destination
Register)............................................... 74
Add Stack Pointer
ADDSP (Add Stack Pointer and Immediate Data)
.......................................................... 241
Add Word Data
ADD (Add Word Data of Source Register to
Destination Register) ............................. 72
ADDC (Add Word Data of Source Register and Carry
Bit to Destination Register) .................... 75
ADDN (Add Word Data of Source Register to
Destination Register) ............................. 76
ADDC
ADDC (Add Word Data of Source Register and Carry
Bit to Destination Register) .................... 75
ADDN
ADDN (Add Immediate Data to Destination Register)
............................................................ 77
ADDN (Add Word Data of Source Register to
Destination Register) ............................. 76
ADDN2 (Add Immediate Data to Destination
Register)............................................... 78
ADDSP
ADDSP (Add Stack Pointer and Immediate Data)
.......................................................... 241
Alignment
Data Restrictions on Word Alignment .................. 11
Program Restrictions on Word Alignment ............ 11
AND
AND (And Word Data of Source Register to Data in
Memory) .............................................. 86
AND (And Word Data of Source Register to
Destination Register) ............................. 85
And Byte Data
ANDB (And Byte Data of Source Register to Data in
Memory) .............................................. 90
And Condition Code
ANDCCR (And Condition Code Register and
Immediate Data).................................. 238
And Half-word Data
ANDH (And Half-word Data of Source Register to
Data in Memory) ................................... 88
278
And Word Data
AND (And Word Data of Source Register to Data in
Memory) .............................................. 86
AND (And Word Data of Source Register to
Destination Register)............................. 85
ANDB
ANDB (And Byte Data of Source Register to Data in
Memory) .............................................. 90
ANDCCR
ANDCCR (And Condition Code Register and
Immediate Data) ................................. 238
ANDH
ANDH (And Half-word Data of Source Register to
Data in Memory) .................................. 88
Arithmetic Shift
ASR (Arithmetic Shift to the Right Direction)
................................................. 144, 145
ASR2 (Arithmetic Shift to the Right Direction)
......................................................... 146
ASR
ASR (Arithmetic Shift to the Right Direction)
................................................. 144, 145
ASR2 (Arithmetic Shift to the Right Direction)
......................................................... 146
B
BANDH
BANDH (And 4-bit Immediate Data to Higher 4 Bits
of Byte Data in Memory) ..................... 108
BANDL
BANDL (And 4-bit Immediate Data to Lower 4 Bits of
Byte Data in Memory)......................... 106
Bcc
Bcc (Branch Relative if Condition Satisfied) ...... 194
Bcc:D (Branch Relative if Condition Satisfied)
......................................................... 203
BEORH
BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of
Byte Data in Memory)......................... 116
BEORL
BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of
Byte Data in Memory)......................... 114
Bit Order
Bit Order and Byte Order.................................... 10
Bit Pattern
Relation between Bit Pattern "Rs" and Register Values
........................................................................ 65