Or (Or Word Data Of Source Register To Destination Register) - Fujitsu FR Family Instruction Manual

CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.18 OR (Or Word Data of Source Register to Destination
Register)
Takes the logical OR of the word data in "Ri" and the word data in "Rj", stores the
results to "Ri".

■ OR (Or Word Data of Source Register to Destination Register)

Assembler format: OR Rj, Ri
Ri or Rj → Ri
Operation:
Flag change:
N:
Z:
V and C: Unchanged
Execution cycles: 1 cycle
Instruction format:
Example: OR R2, R3
92
N Z V C
C C – –
Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Set when the operation result is "0", cleared otherwise.
MSB
1 0 0 1
Instruction bit pattern : 1001 0010 0010 0011
R2
1 1 1 1 0 0 0 0
R3
1 0 1 0 1 0 1 0
N Z V C
CCR
0 0 0 0
Before execution
0 0 1 0 Rj
LSB
Ri
R2
1 1 1 1 0 0 0 0
R3 1 1 1 1 1 0 1 0
N Z V C
CCR
0 0 0 0
After execution