Fujitsu FR Family Instruction Manual page 295

Table A.2-12 Delayed Branching Instructions (20 Instructions)
Mnemonic Format
JMP:D @Ri
CALL:D label12
CALL:D @Ri
RET:D
BNO:D label9
BRA:D label9
BEQ:D label9
BNE:D label9
BC:D label9
BNC:D label9
BN:D label9
BP:D label9
BV:D label9
BNV:D label9
BLT:D label9
BGE:D label9
BLE:D label9
BGT:D label9
BLS:D label9
BHI:D label9
Notes:
• The field "rel8" in the TYPE-D instruction format and the field "rel11" in the TYPE-F format have
the following relation to the values "label9" and "label12" in assembly notation.
→
label9
label12
• Delayed branching instructions are always executed after the following instruction (the delay slot).
• In order to occupy a delay slot, an instruction must satisfy either of the following conditions. Any
other instructions used in this position may not be executed according to definition.
- Instructions other than branching instructions, with the cycle (CYC) column showing the value
"1".
- Instructions with the cycle (CYC) column showing the value "a", "b", "c", or "d".
OP CYC
E 9F-0 1
F D8 1
E 9F-1 1
E 9F-2 1
D F1 1
D F0 1
D F2 1
D F3 1
D F4 1
D F5 1
D F6 1
D F7 1
D F8 1
D F9 1
D FA 1
D FB 1
D FC 1
D FD 1
D FE 1
D FF 1
rel8=(label9 – PC – 2)/2
→
rel11=(label12 – PC – 2)/2
FLAG
NZVC
Ri → PC
– – – –
PC+4 → RP ,PC+2+rel11×2 → PC
– – – –
PC+4 → RP, Ri → PC
– – – –
RP → PC
– – – –
– – – – No branch
PC+2+rel8×2 → PC
– – – –
PC+2+rel8×2 → PC if Z==1
– – – –
PC+2+rel8×2 → PC if Z==0
– – – –
PC+2+rel8×2 → PC if C==1
– – – –
PC+2+rel8×2 → PC if C==0
– – – –
PC+2+rel8×2 → PC if N==1
– – – –
PC+2+rel8×2 → PC if N==0
– – – –
PC+2+rel8×2 → PC if V==1
– – – –
PC+2+rel8×2 → PC if V==0
– – – –
PC+2+rel8×2 → PC if V xor N==1
– – – –
PC+2+rel8×2 → PC if V xor N==0
– – – –
PC+2+rel8×2 → PC if (V xor N) or Z==1
– – – –
PC+2+rel8×2 → PC if (V xor N) or Z==0
– – – –
PC+2+rel8×2 → PC if C or Z==1
– – – –
PC+2+rel8×2 → PC if C or Z==0
– – – –
APPENDIX A Instruction Lists
Operation Remarks
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