Fujitsu FR Family Instruction Manual page 297

Table A.2-16 Other Instructions (16 Instructions)
Mnemonic Format
NOP E
ANDCCR #u8 D
ORCCR #u8 D
STILM #u8 D
ADDSP #s10 D
EXTSB Ri E
EXTUB Ri E
EXTSH Ri E
EXTUH Ri E
LDM0 (reglist) D
LDM1 (reglist) D
STM0 (reglist) D
STM1 (reglist) D
ENTER #u10 D
LEAVE E
XCHB @Rj, Ri A
Notes:
• In the "ADD SP" instruction, the field "s8" in the TYPE-D instruction format has the following
relation to the value "s10" in assembly notation.
→
s10 s8=s10 >> 2
• In the "ENTER" instruction, the field "u8" in the TYPE-D instruction format has the following
relation to the value "u10" in assembly notation.
→
u10 u8=u10 >> 2
• The number of execution cycles for the "LDM0" (reglist) and "LDM1" (reglist) instructions is:
a × (n – 1) + b + 1 cycles, where "n" is the number of registers designated.
• The number of execution cycles for the "STM0" (reglist) and "STM1" (reglist) instructions is:
a × n+1 cycles, where "n" is the number of registers designated.
FLAG
OP CYC
NZVC
9F-A 1 – – – – No change
CCR and u8 → CCR
83 c CCCC
CCR or u8 → CCR
93 c CCCC
– – – – u8 → ILM
87 1
A3 1 – – – – R15 += s10
Sign extension 8 → 32bit
97-8 1 – – – –
Zero extension 8 → 32bit
97-9 1 – – – –
Sign extension 16 → 32bit
97-A 1 – – – –
Zero extension 16 → 32bit
97-B 1 – – – –
(R15) → reglist,
8C See – – – –
notes increment R15
(R15) → reglist,
8D below. – – – –
increment R15
8E See – – – – Decrement R15
reglist → (R15)
notes
8F below. – – – – Decrement R15
reglist → (R15)
– – – – R14 → (R15 – 4),
0F 1+a
R15 – 4 → R14,
R15 – u10 → R15
– – – – R14 + 4 → R15,
9F-9 b
(R15 – 4) → R14
– – – – Ri → TEMP
8A 2a
(Rj) → Ri
TEMP → (Rj)
APPENDIX A Instruction Lists
Operation RMW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
❍
Remarks
Sets "ILM" immediate
value
"ADD SP" instruction
Load multiple R0 to R7
Load multiple R8 to R15
Store multiple R0 to R7
Store multiple R8 to R15
Function entry processing
Function exit processing
Byte data for semaphore
processing
273