Fujitsu FR Family Instruction Manual page 291

Table A.2-5 Multiply/Divide Instructions (10 Instructions)
Mnemonic
MUL Rj,Ri
MULU Rj,Ri
MULH Rj,Ri
MULUH Rj,Ri
DIV0S Ri
DIV0U Ri
DIV1 Ri
DIV2 Ri
DIV3
DIV4S
Table A.2-6 Shift Instructions (9 Instructions)
Mnemonic
LSL Rj, Ri
LSL #u4, Ri
LSL2 #u4, Ri
LSR Rj, Ri
LSR #u4, Ri
LSR2 #u4, Ri
ASR Rj, Ri
ASR #u4, Ri
ASR2 #u4, Ri
Table A.2-7 Immediate Data Transfer Instructions (Immediate Transfer Instructions for Immediate Value
Set or 16-bit or 32-bit Values) (3 Instructions)
Mnemonic
LDI:32 #i32, Ri
LDI:20 #i20, Ri
LDI:8 #i8, Ri
Format OP CYC
A AF 5
A AB 5
A BF 3
A BB 3
E 97-4 1
E 97-5 1
E 97-6 d
E 97-7 1
E 9F-6 1
E 9F-7 1
Format OP CYC
A B6 1
C B4 1
C B5 1
A B2 1
C B0 1
C B1 1
A BA 1
C B8 1
C B9 1
Format OP CYC
E 9F-8 3
C 9B 2
B C0 1
FLAG
Operation
NZVC
Rj × Ri → MDH,MDL
CCC –
Rj × Ri → MDH,MDL
CCC –
Rj × Ri → MDL
CC – –
Rj × Ri → MDL
CC – –
– – – –
– – – –
– C– C
– C– C
– – – –
– – – –
FLAG
Operation
NZVC
Ri << Rj → Ri
CC – C
Ri << u4 → Ri
CC – C
Ri <<{u4+16} → Ri
CC – C
Ri >> Rj → Ri
CC – C
Ri >> u4 → Ri
CC – C
Ri >>{u4+16} → Ri
CC – C
Ri >> Rj → Ri
CC – C
Ri >> u4 → Ri
CC – C
Ri >>{u4+16} → Ri
CC – C
FLAG
Operation
NZVC
i32 → Ri
– – – –
i20 → Ri
– – – –
i8 → Ri
– – – –
APPENDIX A Instruction Lists
Remarks
32bits × 32bits=64bits
Unsigned
16bits × 16bits=32bits
Unsigned
Step operation
32bits/32bits=32bits
Remarks
Logical shift
Logical shift
Arithmetic shift
Remarks
Higher 12 bits are zeros
Higher 24 bits are zeros
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