Fujitsu FR Family Instruction Manual page 22

32-bit microcontroller
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"7.121 ANDCCR (And Condition Code Register and Immediate Data)" is changed.
238
( "Instruction bit pattern : 1000 0011 1111 1110" is added. )
"7.122 ORCCR (Or Condition Code Register and Immediate Data)" is changed.
239
( "Instruction bit pattern : 1001 0011 0001 0000" is added. )
"7.123 STILM (Set Immediate Data to Interrupt Level Mask Register)" is changed.
240
( "Instruction bit pattern : 1000 0111 0001 0100" is added. )
"7.125 EXTSB (Sign Extend from Byte Data to Word Data)" is changed.
242
( "Instruction bit pattern : 1001 0111 1000 0001" is added. )
"7.126 EXTUB (Unsign Extend from Byte Data to Word Data)" is changed.
243
( "Instruction bit pattern : 1001 0111 1001 0001" is changed. )
"7.127 EXTSH (Sign Extend from Byte Data to Word Data)" is changed.
244
( "Instruction bit pattern : 1001 0111 1010 0001" is added. )
"7.128 EXTUH (Unsigned Extend from Byte Data to Word Data)" is changed.
245
( "Instruction bit pattern : 1001 0111 1011 0001" is added. )
"7.133 ENTER (Enter Function)" is changed.
255
( "XXXX XXXX 0000 0011" → "0000 1111 0000 0011" )
"7.134 LEAVE (Leave Function)" is changed.
257
( "Instruction bit pattern : 1001 1111 1001 0000" is addded. )
"7.135 XCHB (Exchange Byte Data)" is chenged.
258
( "extu (Rj) → Ri" → "extu ((Rj)) → Ri" )
"7.135 XCHB (Exchange Byte Data)" is chenged.
259
( "Instruction bit pattern : 1000 1010 0001 0000" is added. )
Changes (For details, refer to main body.)
xviii

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