7.22
EOR (Exclusive Or Word Data of Source Register to
Destination Register)
Takes the logical exclusive OR of the word data in "Ri" and the word data in "Rj", stores
the results to "Ri".
■ EOR (Exclusive Or Word Data of Source Register to Destination Register)
Assembler format:
EOR Rj, Ri
Ri eor Rj → (Ri)
Operation:
Flag change:
N:
Z:
V and C: Unchanged
Execution cycles:
1 cycle
Instruction format:
Example:
EOR R2, R3
N
Z
V
C
C
C
–
–
Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Set when the operation result is "0", cleared otherwise.
MSB
1
0
0
1
Instruction bit pattern : 1001 1010 0010 0011
R2
1 1 1 1 0 0 0 0
R3
1 0 1 0 1 0 1 0
N Z V C
CCR
0 0 0 0
Before execution
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
1
0
1
0
Rj
LSB
Ri
R2
1 1 1 1 0 0 0 0
R3
0 1 0 1 1 0 1 0
N Z V C
CCR
0 0 0 0
After execution
99