Table 3. Segment E Connections; Table 4. Supported Ddr2 Modules - Intel S3000PT - Server Board Motherboard Specification

Functional Architecture
Other features provided by the MCH include the following:
Full support of ECC on the DDR2 memory bus
Twelve deep in-order queue, two deep defer queue
Full support of un-buffered DDR2 ECC DIMMs
Support for 256-MB, 512-MB, 1-GB and 2-GB DDR2 memory modules
3.2.1.2 Segment D PCI-Express x8
In this board, the MCH PCIe Lanes 0~7 are connected to an x8 PCI -E riser connector directly
through the MCH. It can support x1, x4, and x8 PCI-E add-in cards through a riser card.
Lane
Lane 0~7
3.2.1.3 MCH Memory Sub-System Overview
The MCH supports a 72-bit wide memory sub-system that can support a maximum of 8 GB of
DDR2 memory using 2GB DIMMs. This configuration needs external registers for buffering the
memory address and control signals. The four chip selects are registered inside the MCH and
need no external registers fo r chip selects.
The memory interface runs at 533/667MT/s. The memory interface supports a 72 -bit wide
memory array. It uses seventeen address lines (BA [2:0] and MA [13:0]) and supports 256-MB,
512-MB, 1-GB, and 2-GB DRAM densities. The DDR DIMM interface supports single-bit error
correction, and multiple bit error detection .
3.2.1.3.1 DDR2 Configurations
The DDR2 interface supports up to 8 GB of main memory and supports single - and double-
density DIMMs. The DDR2 can be any industry-standard DDR2. The following table shows the
DDR2 DIMM technology supported.
DIMM DIMM
Capacity Organization
256MB 32M x 72
512MB 64M x 72
512MB 64M x 72
1GB 128M x 72
1GB 128M x 72
2GB 256M x 72
10

Table 3. Segment E Connections

Slot 1 (PCI Express* x8)

Table 4. Supported DDR2 Modules

DDR2-533/667 Un-buffered
SDRAM Module Matrix
SDRAM SDRAM
Density Organization
256Mbit 32M x 8
256Mbit 32M x 8
512Mbit 64M x 8
512Mbit 64M x 8
1Gbit 128M x 8
1Gbit 128M x 8
Intel® Server Board S3000PT TPS
Device
# SDRAM
Devices/rows/Banks rows/Banks/column
9 /1 / 4 13 / 2 / 10
18 / 2 / 4 13 / 2 / 10
9 / 1 / 4 14 / 2 / 10
18 / 2 / 4 14 / 2 / 10
9 / 1 / 8 14 / 4 / 10
18 / 2 / 8 14 / 8 / 10
# Address bits
Revision 1.3