Error Logging Via Smi Handler; Smbios Type 15; Logging Format Conventions - Intel S3000PT - Server Board Motherboard Specification

Intel® Server Board S3000PT TPS
PCI PERR error
PCI SERR error
6.1.2

Error Logging via SMI Handler

The SMI handler is used to handle and log system level events. The SMI handler pre -processes
all system errors, even those that are normally considered to generate an NMI.
The SMI handler logs the event to NVRAM. For example, the BIOS programs the hardware to
generate a SMI on a single-bit memory error and logs the error in the NVRAM in terms of a
SMBIOS Type 15. After the BIOS finishes logging the error it will assert the NMI if needed.
6.1.2.1 PCI Bus Error
The PCI bus defines two error pins, PERR# and SERR#. These are used for reporting PCI
parity errors and system errors, respectively.
In the case of PERR#, the PCI bus master has the option to retry the offending transaction, or
to report it using SERR#. All other PCI -related errors are reported by SERR#. All PCI -to-PCI
bridges are configured so that they generate a SERR# on the primary interface wh enever there
is a SERR# on the secondary side .
6.1.2.2 PCI Express* Errors
All uncorrectable PCI Express* errors are logged as PCI system errors and promoted to an
NMI. All correctable PCI Express errors are not logged.
6.1.2.3 Memory Errors
The hardware is programmed t o generate an SMI on correctable data errors in the memory
array. The SMI handler records the error to the NVRAM. The uncorrectable errors may have
corrupted the contents of SMRAM. The SMI handler will log the error to the NVRAM if the
SMRAM contents are still valid.
6.1.3

SMBIOS Type 15

Errors are logged to the NVRAM in terms of the SMBIOS Type 15 (System Event Log ). Refer to
the SMBIOS Specification, version 2.4 for more detailed information. The format of the records
is also defined in the following section.
6.1.4

Logging Format Conventions

The BIOS logs an error into the NVRAM area with the following record format, which is also
defined in the SMBIOS Specification, version 2.3.4.
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PERR error happens on PCI bus
SERR error happens on PCI bus
Error Reporting and Handling
POST / Runtime
POST / Runtime
Revision 1.3