Table 9. Pci Interrupt Routing/Sharing; Table 10. Interrupt Definitions - Intel S3000PT - Server Board Motherboard Specification

Intel® Server Board S3000PT TPS
Interrupt
ATIES 1000
3.4.2.2 APIC Interrupt Routing
For APIC mode, the server board interrupt architecture incorporates three Intel
devices to manage and broadcast interrupts to local APICs in each processor. The Intel® I/O
APICs monitor each interrupt on each PCI device, including PCI slots in addition to the ISA
compatibility interrupts IRQ (0-15).
When an interrupt occurs, a message corresponding to the interrupt is sent across a three -wire
serial interface to the local APICs. The APIC bus minimizes interrupt latency time for
compatibility interrupt sources. The I/O APICs can also supply greater than 16 interrupt levels to
the processor(s). This APIC bus consists of an APIC clock and two bi -directional data lines.
3.4.2.3 Legacy Interrupt Sources
The following table recommends the logical interrupt mapping of interrupt sourc es on the board.
The actual interrupt map is defined using configuration registers in the Intel® ICH7R controller.
ISA Interrupt
INTR Processor interrupt
NMI NMI to processor
IRQ0 System timer
IRQ1 Keyboard interrupt
IRQ2 Slave PIC
IRQ3 Serial port 1 interrupt from Super I/O* device, user-configurable
IRQ4 Serial port 1 interrupt from Super I/O* device, user-configurable
IRQ5
IRQ6 Floppy disk
IRQ7 Generic
IRQ8_L Active low RTC interrupt
IRQ9 SCI*
IRQ10 Generic
IRQ11 Generic
IRQ12 Mouse interrupt
IRQ13
Floating point processor
IRQ14 Compatibility IDE interrupt from prim ary channel IDE devices 0 and 1
IRQ15 Secondary IDE cable
SMI* System Management Interrupt. General -purpose indicator sourced by the Intel® ICH7R
Controller to the processors.
Revision 1.3

Table 9. PCI Interrupt Routing/Sharing

INT A
PIRQC

Table 10. Interrupt Definitions

Description
Functional Architecture
INT B INT C
®
INT D
I/O APIC
17