Interrupt Routing; Table 7. Segment A Configuration Ids; Table 8. Segment A Arbitration Connections - Intel S3000PT - Server Board Motherboard Specification

Functional Architecture
3.4.1.1.1 Device IDs (IDSEL)
Each device under the PCI hub bridge has its IDSEL signal connected to one bit of AD (31:16),
which acts as a chip select on the PCI bus segment in configuration cycles. This determines a
unique PCI device ID value for use in configuration cycles. The following table shows the bit to
which each IDSEL signal is attached for Segment A devices and the corresponding device
description.
IDSEL Value
20
3.4.1.1.2 Segment A Arbitration
PCI Segment A supports two PCI devices: the Intel® ICH7R and one PCI bus master (NIC). All
PCI masters must arbitrate for PCI access, using resources supplied by the Intel® ICH7 R. The
host bridge PCI interface (ICH7 R) arbitration lines REQx* and GNTx* are a special case in that
they are internal to the host bridge. The following table defines the arbitration connections.
Server Board Signals
PCI REQ_N4/GNT_N4
3.4.2

Interrupt Routing

The board interrupt architecture accommodates both PC -compatible PIC mode and APIC mode
interrupts through use of the integrated I/O APICs in the Intel® ICH7R controller.
3.4.2.1 Legacy Interrupt Routing
For PC-compatible mode, the Intel® ICH7R controller provides two 82C59-compatible interrupt
controllers. The two controllers are cascaded with interrupt levels 8 -15 entering on level 2 of the
primary interrupt controller (standard PC configuration). A single interrupt signal is presented to
the processors, to which only one processor will respond for servicing. The Intel® ICH7R
contains configuration registers that define which interrupt source logically maps to I/O APIC
INTx pins.
The Intel® ICH7R controller handles both PCI and IRQ interrupts. The Intel® ICH7R translates
these to the APIC bus. The numbers in the following table indicate the Intel® ICH7R PCI
interrupt input pin to which the associated device interrupt (INTA, INTB, INTC, INTD, INT E,
INTF, INTG, INTH for PCI bus and PXIRQ0, PXIRQ1, PXIRQ2, PXIRQ3 for PCI-X bus) is
connected. The Intel® ICH7R I/O APIC exists on the I/O APIC bus with the processors.
16

Table 7. Segment A Configuration IDs

ATI* ES1000 video controller

Table 8. Segment A Arbitration Connections

ATI* ES1000 video controller
Intel® Server Board S3000PT TPS
Device
Device
Revision 1.3