Tables
1-1
1-2
Related Documents ................................................................................................. 18
2-1
2-2
2-3
2-4
Reference Clock...................................................................................................... 33
4-1
System States........................................................................................................ 43
4-2
4-3
4-4
PCIe Link States ..................................................................................................... 44
4-5
DMI States ............................................................................................................ 44
4-6
4-7
4-8
4-9
6-1
6-2
Memory Channel A.................................................................................................. 60
6-3
Memory Channel B.................................................................................................. 61
6-4
6-5
6-6
®
6-7
6-8
6-9
PLL Signals ............................................................................................................ 64
6-10 TAP Signals............................................................................................................ 64
6-12 Power Sequencing .................................................................................................. 65
6-14 Sense Pins ............................................................................................................. 66
6-15 Ground and NCTF ................................................................................................... 66
7-1
7-2
VCCSA_VID configuration ........................................................................................ 74
7-3
Signal Groups 1 ...................................................................................................... 75
7-4
7-5
7-6
7-7
7-8
7-9
8-1
9-1
9-2
Datasheet, Volume 1
7