Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 1 01-2011 Datasheet page 17

Introduction
PEG
Processor
Processor Core
Processor Graphics
Rank
SCI
Storage Conditions
TAC
TDP
V
AXG
V
CC
V
CCIO
V
CCPLL
V
CCSA
V
DDQ
VLD
V
SS
x1
x16
x4
x8
Datasheet, Volume 1
Term
PCI Express* Graphics. External Graphics using PCI Express* Architecture. A
high-speed serial interface whose configuration is software compatible with the
existing PCI specifications.
The 64-bit, single-core or multi-core component (package).
The term "processor core" refers to Si die itself which can contain multiple
execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache.
®
Intel Processor Graphics
A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC.
These devices are usually, but not always, mounted on a single side of a SO-
DIMM.
System Control Interrupt. Used in ACPI protocol.
A non-operational state. The processor may be installed in a platform, in a tray,
or loose. Processors may be sealed in packaging or exposed to free air. Under
these conditions, processor landings should not be connected to any supply
voltages, have any I/Os biased or receive any clocks. Upon exposure to "free air"
(that is, unsealed packaging or a device removed from packaging material) the
processor must be handled in accordance with moisture sensitivity labeling
(MSL) as indicated on the packaging material.
Thermal Averaging Constant.
Thermal Design Power.
Graphics core power supply.
Processor core power supply.
High Frequency I/O logic power supply
PLL power supply
System Agent (memory controller, DMI, PCIe controllers, and display engine)
power supply
DDR3 power supply.
Variable Length Decoding.
Processor ground.
Refers to a Link or Port with one Physical Lane.
Refers to a Link or Port with sixteen Physical Lanes.
Refers to a Link or Port with four Physical Lanes.
Refers to a Link or Port with eight Physical Lanes.
Description
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