Table 136. Ipmb Header Pin-Out; Table 137. Sata Host I - Intel SC5299BRP Technical Product Specification

®
Intel Entry Server Chassis SC5299-E TPS
4.3.2.9 Clock Generation and Distribution
The 6HDD SATA HSBP provides one clock source. A 20-MHz oscillator provides the clock to
the GEM424 controller.
4.3.2.10 IPMB Header - IPMB
The following table defines the pin-out of the 4-pin IPMB Header (J13).
4.3.2.11 SATA Host I
The following table defines the pin-out of the 3-pin SATA Host I
4.3.2.12 Board Layout
The following figure shows the board layout and connector placement of the SATA hot-swap
backplane.
Note: Secondary side is mirrored.
Revision 3.1

Table 136. IPMB Header Pin-out

Pin Signal Name
2
1 I C Address
Control
2 BP_I2C_SCL
3 GND
4 BP_I2C_SDA
C Header - I2C_1
2

Table 137. SATA Host I

Pin Signal Name
1 BP_I2C_SDA
2 GND
3 BP_I2C_SCL
Intel order number D37594-005
Peripheral and Hard Drive Support
Description
IPMI interface address selection.
Primary = 0xC0, Secondary = 0xC2
Clock
Data
2
C Header (JP1).
2
C Header Pin-out
Description
Data
Clock
117