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Intel
Entry Server Chassis SC5299-E TPS
2.1.5.7
Capacitive Loading
The power supply is stable and meets all requirements with the following capacitive loading
ranges.
2.1.5.8
Closed Loop Stability
The power supply is unconditionally stable under all line/load/transient load conditions, including
capacitive load ranges. A minimum of: 45 degrees phase margin and -8dB-gain margin is
required. Closed-loop stability is ensured at the maximum and minimum loads as applicable.
2.1.5.9
Ripple/Noise
The maximum allowed ripple/noise output of the power supply is defined in the following table.
This is measured over a bandwidth of 0 Hz to 20 MHz at the power supply output connectors.
+3.3V
50mVp-p
2.1.5.10
Timing Requirements
The timing requirements for power supply operation are as follows. The output voltages must
rise from 10% to within regulation limits (T
allowed to rise from 1.0 to 70ms. The +3.3V, +5V and +12V output voltages should start to rise
approximately at the same time. All outputs must rise monotonically. The +5V output needs to
be greater than the +3.3V output during any point of the voltage rise. The +5V output must
never be greater than the +3.3V output by more than 2.25V. Each output voltage shall reach
regulation within 50ms (T
voltage shall fall out of regulation within 400msec (T
following figure shows the timing requirements for the power supply being turned on and off via
the AC input, with PSON held low and the PSON signal, with the AC input applied.
Revision 3.1
Table 14. Capacitive Loading Conditions
Output
MIN
+3.3V
250
+5V
400
+12V(1, 2)
500 each
-12V
1
+5VSB
20
Table 15. Ripple and Noise
+5V
+12V1/2
50mVp-p
120mVp-p
vout_rise
) of each other during turn on of the power supply. Each output
vout_on
Intel order number D37594-005
MAX
6,800
4,700
11,000
350
350
-12V
120mVp-p
) within 2 to 20ms, except for 5VSB which is
) of each other during turn off. The
vout_off
Power Sub-system
Units
F
F
F
F
F
+5VSB
50mVp-p
19
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