Table 117. Voltage Regulation Limits; Table 118. Transient Load Requirements; Table 119. Capacitive Loading Conditions - Intel SC5299BRP Technical Product Specification

Power Sub-system
Parameter
+ 3.3V
+ 5V
+ 12V1
+ 12V2
+12V3
+12V4
- 12V
+ 5VSB
2.5.8.6 Dynamic Loading
The output voltages remain within limits specified for the step loading and capacitive loading, as
shown in the following table. The load transient repetition rate is tested between 50 Hz and 5
kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test
specification. The step load may occur anywhere between the MIN load and MAX load
conditions.
Output
+3.3V
+5V
+12V
+5VSB
1. Step loads on each 12V output may happen simultaneously.
2.5.8.7 Capactive Loading
The power supply is stable and meets all requirements with the following capacitive loading
ranges.
+3.3V
96

Table 117. Voltage Regulation Limits

Tolerance MIN
- 5%/+5% +3.14
- 5%/+5% +4.75
- 5%/+5% +11.40
- 5%/+5% +11.40
- 5%/+5% +11.40
- 5%/+5% +11.40
- 5%/+9% -11.40
- 5%/+5% +4.75

Table 118. Transient Load Requirements

Step Load Size
1
7.0A
7.0A
25A
0.5A

Table 119. Capacitive Loading Conditions

Output MIN
250
Intel order number D37594-005
®
Intel Entry Server Chassis SC5299-E TPS
NOM MAX
+3.30 +3.46
+5.00 +5.25
+12.00 +12.60
+12.00 +12.60
+12.00 +12.60
+12.00 +12.60
-12.00 -13.08
+5.00 +5.25
Load Slew Rate Test Capacitive Load
0.25 A/ sec
0.25 A/ sec
0.25 A/ sec
0.25 A/ sec
MAX Units
6800
F
Units
V
rms
V
rms
V
rms
V
rms
V
rms
V
rms
V
rms
V
rms
4700 F
1000 F
4700 F
20 F
Revision 3.1