Figure 11. Output Voltage Timing; Table 45. Turn On/Off Timing - Intel SC5299BRP Technical Product Specification

Power Sub-system
V out
10% V out
V1
V2
V3
V4
Item
T Delay from AC being applied to 5VSB being within
sb_on_delay
regulation.
T Delay from AC being applied to all output voltages being
ac_on_delay
within regulation.
T Time all output voltages stay within regulation after loss of
vout_holdup
AC.
T Delay from loss of AC to de-assertion of PWOK
pwok_holdup
T Delay from PSON
pson_on_delay
limits.
T Delay from PSON
pson_pwok
T Delay from output voltages within regulation limits to PWOK
pwok_on
asserted at turn on.
T Delay from PWOK de-asserted to output voltages (3.3V, 5V,
pwok_off
12V, -12V) dropping out of regulation limits.
T Duration of PWOK being in the de-asserted state during an
pwok_low
off/on cycle using AC or the PSON signal.
40
T vout_rise
T vout_on

Figure 11. Output Voltage Timing

Table 45. Turn On/Off Timing

Description
#
active to output voltages within regulation
#
deactive to PWOK being de-asserted.
Intel order number D37594-005
®
Intel Entry Server Chassis SC5299-E TPS
T vout_off
Minimum
21
20
5
100
1
100
TP02313
Maximum Units
msec
1500
msec
2500
msec
msec
msec
400
50 msec
msec
500
msec
msec
Revision 3.1