Simons Voss Technologies SmartRelay 3 Manual page 125

SmartRelay 3 system (Manual)
Signal timing
tCLK tCLK tCLK tCLK
CLK
DAT
CLS
Bit 0 0
tCLS-
Descrip-
Time
tion
Time
between
activation
t of the CLS
CLS-
signal and
first data
bit
Clock
t
CLK
period
Set-up
t time for
S
data bit
Clock set
to "low"
t
C0
level
(clock low)
tCLK tCLK
1 1 0 1
tS tC0
"Card is loaded"
"Data is being transmitted"
Min. Typ.
8 12
290 320
50 100
50 100
10. SREL3 ADV in LSM
125 / 189
tCLK tCLK
0 0 1
tCLS+
Max. Unit
20 ms
350 µs
150 µs
150 µs