Operation - Analog Devices MAX96752 User Manual

configurations, a color lookup table (LUT) for gamma correction, and programmable spread-spectrum clocking
(SSC).
oLDI output configurations:
• Single port (4 or 8 lanes) or dual port (2x4 lanes)
• 1x4, 2x4, or 1x8 oLDI output lane configurations
Each port supports pixel clock rates up to 150MHz (300MHz in dual port mode). Refer to the
Optimization subsection for additional information.

Operation

GMSL2 oLDI deserializers receive GMSL data from the serial link and convert it to video data. The video data is then
transmitted by the video pipes and mapped to ports A and/or B of the output interface. The output video interface
has user-configurable port arrangements and can transmit single or dual oLDI video in either oLDI or VESA formats
(see LVDS Data Mapping
Table below contains the oLDI output video interface pin numbers, names, and descriptions.
Table 5. Dual oLDI Interface Pin Descriptions
Pin Number Pin Name
30 TxOUT_A3+
31 TxOUT_A3-
32 TxOUT_A2+
33 TxOUT_A2-
36 TxOUT_A1+
37 TxOUT_A1-
38 TxOUT_A0+
39 TxOUT_A0-
34 TxCLK_OUTA+
35 TxCLK_OUTA-
46 TxOUT_B3+
47 TxOUT_B3-
48 TxOUT_B2+
49 TxOUT_B2-
52 TxOUT_B1+
53 TxOUT_B1-
54 TxOUT_B0+
55 TxOUT_B0-
50 TxCLK_OUTB+
51 TxCLK_OUTA-
The GMSL2 oLDI deserializer generates the oLDI clock output from the tracked and measured clock frequency of
the video input at the connected serializer.
www.analog.com
below).
Function
LVDS Data Output Port A
LVDS Data Output Port A
LVDS Data Output Port A
LVDS Data Output Port A
LVDS Data Output Port A
LVDS Data Output Port A
LVDS Data Output Port A
LVDS Data Output Port A
LVDS Clock Output Port A
LVDS Clock Output Port A
LVDS Data Output Port B
LVDS Data Output Port B
LVDS Data Output Port B
LVDS Data Output Port B
LVDS Data Output Port B
LVDS Data Output Port B
LVDS Data Output Port B
LVDS Data Output Port B
LVDS Clock Output Port B
LVDS Clock Output Port B
Figure 7 shows the LVDS pulse positions with the oLDI clock.
Bandwidth Efficiency
Analog Devices | 10