Programming Examples; Stream At Single Oldi Output - Analog Devices MAX96752 User Manual

PRBS registers are presented in
Table 8. PRBS Registers
Register
Bitfield
Address
0x1CD VPRBS_FAIL
0x1CD VPRBS_CHK_EN
Table 9 contains registers used to enable the LUT; reference the
information.
Table 9. LUT Registers
Register
Bitfield
Address
0x1CD LUT_C_EN
0x1CD LUT_B_EN
0x1CD LUT_EN_A
Sync signals can be viewed on GPIO01 if enabled with the registers in
sheet for pin-mapping details.
Table 10.
GPIO Sync Signal Output
Register
Bitfield
Address
0x1CF VS_OUT_EN

Programming Examples

Stream at Single oLDI Output

Perform the following writes in the oLDI deserializer:
OLDI_OUTSEL = Select LVDS output port (A or B) to put the LVDS video data
OLDI_FORMAT = Select the mapping format (oLDI or VESA) for the LVDS port
OLDI_4TH_LANE = Select 24- or 18-bit output (i.e., 4- or 3-lane output port)
OLDI_DUP = Select if the same video should be duplicated on both LVDS ports
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Table 8.
Description
Video PRSB pass/fail.
Enables video PRBS checker.
Description
Enables Color C lookup table (LUT)
[23:16]
Enables Color B lookup table (LUT)
[15:8]
Enables Color A lookup table (LUT)
[7:0]
Description
Output VSYNC from GPIO.
Decode
0b0: Video PRBS check passed
0b1: Video PRBS check failed
0b0: Video PRBS checker disabled
0b1: Video PRBS checker enabled
Color Lookup Table (LUT)
Decode
0b0: Color C LUT disabled
0b1: Color C LUT enabled
0b0: Color B LUT disabled
0b1: Color B LUT enabled
0b0: Color A LUT disabled
0b1: Color A LUT enabled
Table 10. Reference the device-specific data
Decode
0b0: VSYNC not output
0b1: Output VSYNC from GPIO
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