Undervoltage Monitoring Of V; Monitoring Details; Vdd18; Dd18 - Analog Devices MAX96752 User Manual

Undervoltage Monitoring of V

An undervoltage condition on V
between devices. Refer to the data sheet specific to the part number to verify the specified V
threshold for a given device.
In the case of an undervoltage condition, the power manager triggers a reset of the digital core and resets all
registers powered by V
DD
a brownout does not result in corruption of the registers.
The presence of an undervoltage event is recorded via two status flags:
Table 22. V Undervoltage Status Flags
DD
Bitfield
VDDBAD_STATUS[1], VDDBAD_STATUS[0]
CMP_STATUS[2]
The memory that maintains the
as a result, they are persistent following a reset triggered by a V
undervoltage event to be reported following the recovery of the V
flags, VDDBAD_INT_FLAG
To clear VDDBAD_INT_FLAG, the associated
VDDBAD_STATUS bits are cleared,
process to clear VDDCMP_INT_FLAG
reading).
V

Monitoring Details

DD18

All GMSL2 devices include undervoltage monitoring of V

Undervoltage Monitoring of V

An undervoltage condition on V
some between devices. Refer to the data sheet specific to the part number to verify the specified V
threshold for a given device.
In the case of an undervoltage condition, the status register bit
flagged using the VDDCMP_INT_FLAG, which can be configured to drive the fault condition to the ERRB pin. The
error status is cleared by first reading
V Monitoring Details
DDIO
V includes undervoltage monitoring only; overvoltage monitoring is not available. This monitoring is available
DDIO
to all GMSL2 devices. An undervoltage condition on V
precise threshold varies some between devices. Refer to the data sheet specific to the part number to verify the
specified V undervoltage threshold for a given device.
DDIO
In the case of an undervoltage condition, the status register bit CMP_STATUS[1] is latched low. The error can be
flagged using the VDDCMP_INT_FLAG, which can be configured to drive the fault condition to the ERRB pin. The
error status is cleared by first reading
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DD
nominally occurs when VDD < 0.82V. Note that the precise threshold varies some
DD
. When power has recovered, the reset is released. The reset of the digital core ensures that
VDDBAD_STATUS
and VDDCMP_INT_FLAG, can drive ERRB low to alert the system of a brownout.
VDDBAD_STATUS
VDDBAD_INT_FLAG
is similar (i.e., the associated
DD18
is nominally flagged when V
DD18
CMP_STATUS[0]
CMP_STATUS[1]
Description
Latched high following undervoltage event.
Latched low following undervoltage.
and CMP_STATUS[2] bits is powered by the 1.8V power supply;
undervoltage event. This enables a V
DD
power supply, and the associated interrupt
DD
bits must be read first to clear. After the
can then be read, at which point the flag will be cleared. The
CMP_STATUS
.
DD18
< 1.625V. Note that the precise threshold varies
DD18
CMP_STATUS[0]
and then reading VDDCMP_INT_FLAG.
is nominally flagged when V
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and then reading VDDCMP_INT_FLAG.
undervoltage
DD
DD
bit must be cleared first via
undervoltage
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is latched low. The error can be
< 1.625V. Note that the
DDIO
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