Output Programming; Color Lookup Table (Lut); Spread-Spectrum Clocking - Analog Devices MAX96752 User Manual

PREVIOUS CYCLE
TxOUT0_A
TxOUT1_A
TxOUT2_A
TxOUT3_A
TxOUT0_B
TxOUT1_B
TxOUT2_B
TxOUT3_B

Output Programming

• Output ports are configurable as 1x4, 1x8, or 2x4 lanes. Refer to the
details related to this block.
• oLDI ports can be configured as 4-lane (for RGB888) or 3-lane (for RGB666) with the OLDI_4TH_LANE register bit.
• The oLDI output lanes can be inverted and/or swapped. The LANE_SEL_* registers select the output pin
mapping for the port and lane designated by the register name; the LANE_INV_* registers invert the polarity of
the port and lane designated by the register name.
• Vertical sync (VS) can be viewed on GPIO01. An optional single-cycle glitch filter is enabled with the VS_OUT_EN
register bit.

Color Lookup Table (LUT)

The LUT enables 1:1 translation of 8-bit RGB color input data to any 8-bit RGB color output values. The feature is
primarily intended for color filtering and gamma correction. The LUT consists of three discrete color channels that
accept 8-bit wide entry for each color (i.e., red, green, and blue) with 256-entry depth. Refer to the
Table (LUT) section for additional information and configuration details.

Spread-Spectrum Clocking

The oLDI output port can be programmed to have 0.5% center spread-spectrum clocking (SSC) with a 20kHz to
40kHz triangular modulation frequency. It is possible to program the spread-spectrum percentage up to 4% with
the config_spread_bit_ratio bitfield (register DPLL_3).
Note: oLDI SSC mode programming is independent of the GMSL high-speed clock SSC mode.
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CURRENT CYCLE
OG0 OR5 OR4
OB1 OB0 OG5
DE VS HS
XX OB7 OB6
EG0 ER5 ER4
EB1 EB0 EG5
DE VS HS
XX EB7 EB6
Figure 11. Dual oLDI Port Mapping (VESA/Format 2)
CLK
OR3 OR2 OR1
OG4 OG3 OG2
OB5 OB4 OB3
OG7 OG6 OR7
ER3 ER2 ER1
EG4 EG3 EG2
EB5 EB4 EB3
EG7 EG6 ER7
Configuration
OR0
OG1
OB2
OR6
ER0
EG1
EB2
ER6
section for programming
Color Lookup
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