Lvds Data Mapping; Single Pixel Per Clock Output - Analog Devices MAX96752 User Manual

(TXCLKOUT+)-(TXCLKOUT-)
(TXOUT_+)-(TXOUT_-)
GMSL2 oLDI deserializers can be configured as single port (4 or 8 lanes) or dual port (2x4 lanes) to accommodate a
range of display applications. Each port supports pixel clock (PCLK) rates up to 150MHz and a combined PCLK of
300MHz in Dual-port mode. Video data can be mapped to oLDI ports A, B, or both. Additionally, video lanes can be
inverted and/or swapped to assist in compatibility with display interfaces. Both oLDI and VESA output formats are
supported.

LVDS Data Mapping

The following sections provide the LVDS data mapping for single- and dual-port oLDI output.

Single Pixel per Clock Output

TxOUT0 G2
TxOUT1 B3
TxOUT2 DE
TxOUT3 XX
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tPPOS0
tPPOS1
tPPOS2
tPPOS3
tPPOS4
tPPOS5
tPPOS6
Figure 7. LVDS pulse positions
R7 R6
B2 G7
VS HS
B1 B0
Figure 8. Single oLDI Port Mapping (oLDI/Format 1)
CLK
R5 R4
G6 G5
B7 B6
G1 G0
R3 R2
G4 G3
B5 B4
R1 R0
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