About The User Guide; Device Overview; Start-Up And Programming Sequence; Register Configuration Sequencing - Max96752 - Analog Devices MAX96752 User Manual

About the User Guide

This user guide is intended to be used in conjunction with other documents such as the device specific data sheets,
errata documents, and other user and design guides. It provides explanations, examples, and instructions to help
setup video configurations and use various features.
Examples shown in this guide do not consider errata fixes that may be necessary to ensure reliable operation in
production. To obtain errata documents, on the Analog Devices website, search for a specific part, and review the
Documentation section. Make sure to include any relevant errata writes in the final production software. In
addition to the errata, it is also important to have the latest revision of the GMSL device for testing.

Device Overview

GMSL2 serial links use packet-based, bidirectional architecture with forward and reverse channels. The forward
channel transfers data from the serializer to the deserializer; the reverse channel transfers data from the
deserializer to the serializer. GMSL2 devices have a forward serial bit rate of 6Gbps or 3Gbps and reverse channel
serial bit rate of 187.5Mbps. See below for supported data rates/features by part number.
The MAX96752 is a full-featured GMSL2 Deserializer device. The MAX96752 is capable of 6Gbps or 3Gbps forward
link rate (selectable by pulling up or down the CXTP pin and selectable with register writes). This device has a
187.5Mbps reverse direction rate.
Table 1. Comparison of the MAX96752 Family High Level Features
Part Number Forward Link Coax/STP Output GMSL Links ASIL Rating
Rate
MAX96752 3 or 6Gbps Coax or STP Dual oLDI 2 B
*Note: This is a not a complete list of device features. Please see the device datasheets for all feature details.
The MAX96752 has 5 two-state configuration pins for bootstrapping the device address, GMSL link rate, STP/COAX
modes, and I2C/UART Control Channel Modes.
CXTP pin selects coaxial operation at 6Gbps when set high or selects shielded-twisted-pair operational mode at
3Gbps when set low.
I2CSEL pin selects I2C operation of the Primary Control Channel when set high or selects UART operation of the
Primary Control Channel when set low.
ADD0, ADD1, and ADD2 pins allow configuration of different device addresses.

Start-up and Programming Sequence

Register Configuration Sequencing – MAX96752
Aside from the sequencing required for the GMSL link and video throughput, there are sequencing requirements for
the register configurations of features in GMSL devices. The register configuration sequences are divided into
groups. The configuration groups must be done in sequence as described below, but the sequence of
configurations within each group is flexible.
Table 2. Configuration Sequencing
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