Analog Devices MAX96752 User Manual page 22

lanes. It is not recommended to change the default settings of these registers unless the TCON or the timing
converter device requires such custom changes.
Table 7. oLDI Output Polarity Inversion and Pin Mapping Registers
Register
Bitfield
Address
0x1D0 LANE_INV_B0
0x1D0 LANE_INV_A0
0x1D1 LANE_INV_B1
0x1D1 LANE_INV_A1
0x1D0 LANE_SEL_B0[2:0]
0x1D0 LANE_SEL_A0[2:0]
0x1D1 LANE_SEL_B1[2:0]
0x1D1 LANE_SEL_A1[2:0]
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Description
Lane B0 polarity inversion
Lane A0 polarity inversion
Lane B1 polarity inversion
Lane A1 polarity inversion
Selects oLDI Port B Lane 0 output
pins
Selects oLDI Port A Lane 0 output
pins
Selects oLDI Port B Lane 1 output
pins
Selects oLDI Port A Lane 1 output
pins
Decode
0b0: Lane polarity not inverted
0b1: Lane polarity inverted
0b0: Lane polarity not inverted
0b1: Lane polarity inverted
0b0: Lane polarity not inverted
0b1: Lane polarity inverted
0b0: Lane polarity not inverted
0b1: Lane polarity inverted
0b000: Output from B0
0b001: Output from B1
0b010: Output from B2
0b011: Output from B3
0b100: Output from BCLK
0b101: Reserved
0b110: Reserved
0b111: Reserved
0b000: Output from A0
0b001: Output from A1
0b010: Output from A2
0b011: Output from A3
0b100: Output from ACLK
0b101: Reserved
0b110: Reserved
0b111: Reserved
0b000: Output from B0
0b001: Output from B1
0b010: Output from B2
0b011: Output from B3
0b100: Output from BCLK
0b101: Reserved
0b110: Reserved
0b111: Reserved
0b000: Output from A0
0b001: Output from A1
0b010: Output from A2
0b011: Output from A3
0b100: Output from ACLK
0b101: Reserved
0b110: Reserved
0b111: Reserved
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