Reset (Power Down/Sleep); Boot - Analog Devices MAX96752 User Manual

Figure 28. Power Manager State Diagrams

Reset (Power Down/Sleep)

Power down and sleep are two sub-states of the reset state.
The device will enter the power down state if the PWDNB pin is asserted (low), VDD_sw falls below the internally set
threshold, or if any other supply falls below the associated POR value. In power down, all registers in the digital
core revert to default reset values. Power failure latches are retained unless V falls too low. De-asserting PWDNB
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(high) releases the chip from the power down state and into the boot state.
Sleep is a low-power consumption state that preserves the configurations and settings saved in the previous state
and enables a much faster return to running operation than from power down. When the device is in the run state,
the system (µC/SoC) can initiate sleep state with an I 2 C/UART command (SLEEP = 1). Sleep mode is entered
automatically after the retention memory is loaded following the SLEEP=1 command. In the sleep state, the V
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supply must be continuously maintained to ensure that previous configurations and settings are preserved. It is
recommended that all other supplies be maintained during Sleep mode to simplify the sleep and wakeup
sequences.

BOOT

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