Mfp/Cfg Pin Setup For Spi; Spi Setup Registers - Analog Devices MAX96752 User Manual

External mosi
miso
SPI
Main
External
SPI
Subordinate
mosi
External
miso
SPI
Subordinate

MFP/CFG Pin Setup for SPI

• Refer to the latest device data sheets for SPI MFP pins. Some MFP pins may have default alternate functions that
must be disabled before enabling SPI. MFP status tool in the GMSL GUI can be used to verify the MFP functions
that are enabled/disabled. If any of the SPI pins are also used as CFG pins, do not let any external SPI devices
pull the CFG pins up or down until the GMSL devices power up and the CFG pins are latched. Power on the GMSL
parts with the external SPI main device not connected or not pulling on the CFG pins; otherwise, the GMSL part
will boot-up into an unwanted configuration.
• RO (Read Only) is an input bit that determines if the SPI subordinate is in Read or Write mode.
• BNE (Buffer Not Empty) is an output bit that shows the receive FIFO state. BNE is low when the buffer is empty.
BNE is high when there is data in the buffer. This bit is used to determine the status of the buffer for data
transfers and avoiding buffer overflow.

SPI Setup Registers

The table below shows some of the important setup registers for enabling SPI interface. Register block in the data
sheet will have additional details for configuring the SPI main, subordinate, SCLK timings, etc.). See the
programming script in the section below as an example.
Table 14.
MAX96752 SPI Register Settings
Register Bitfield Name
0x160 SPI_EN
www.analog.com
sck
Pin
Control
ro
SPI
bne
Subordinate
SPI
Main
ss0
ss1
Pin
Control
sck
Figure 17. GMSL2 SPI Architecture
Bits
0
SPI GMSL2
Packet Tx
SPI GMSL2
Packet Rx
SPI GMSL2
Packet Tx
SPI GMSL2
Packet Rx
Default Value
0 0 = SPI not enabled
GMSL2
spi_gmsl2
GMSL2
spi_gmsl2
Description
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