Clock Configuration - Alinx AX7Z035B User Manual

AX7Z035B User Manual
Signal Name
MMC_CCLK
MMC_CMD
MMC_D0
MMC_D1
MMC_D2
MMC_D3

2.6 Clock Configuration

The core system respectively provides reference clocks for the PS system, the PL
logic, and the GTX transceiver, allowing the PS system and PL logic to work
independently. The schematic diagram of the clock circuit design is shown in Figure
2-6-1:
PS system clock source
The ZYNQ chip provides a 33.333MHz clock input to the PS via the X4 crystal on
the board. The input of the clock is connected to the pin of the BANK500
PS_CLK_500 of the ZYNQ chip. The schematic diagram is shown in Figure 2-6-2:
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ZYNQ Pin Name
PS_MIO48_501
PS_MIO47_501
PS_MIO46_501
PS_MIO49_501
PS_MIO50_501
PS_MIO51_501
Figure 2-6-1: Core board clock source
ZYNQ Pin Number
B21
B19
E17
A18
B22
B20
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