Alinx AX7Z035B User Manual page 38

AX7Z035B User Manual
BANK501. The Ethernet PHY chip on the PL end is connected to the IO of BANK35.
The JL2121 chip supports a 10/100/1000 Mbps network transmission rate and
communicates data with the MAC layer of the Zynq7000 system through the RGMII
interface. JL2121D supports MDI/MDX
adaptations, Master/Slave self-adaptation, and supports MDIO bus for PHY register
management.
JL2121 will detect the level status of specific IO when powered on to determine
its own operating mode. Table 3-3-1 describes the default setting of the GPHY chip
after power on.
Configuration
Pin
RXD3_ADR0
RXC_ADR1
RXCTL_ADR2
RXD1_TXDLY
RXD0_RXDLY
When the network is connected to a Gigabit Ethernet, ZYNQ and PHY chip
JL2121 communicate over the RGMII bus for data transmission, the transmission
clock is 125Mhz, and data is sampled on the rising edge and falling edge of the
clock.
When the network is connected to 100 Gigabit Ethernet, ZYNQ and PHY chip
JL2121 communicate over the RMII bus for data transmission, and the transmission
clock is 25Mhz. Data is sampled on the rising edge and falling edge of the clock.
Figure 3-3-1 shows the connection diagram of the PS Ethernet PHY chip.
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Description
PHY address in MDIO/MDC
mode
TX clock 2ns delay
RX clock 2ns delay
Table 3-3-1: PHY chip default configuration value
self-adaptation, various
Configuration Value
PHY Address is 001
speed self-
Delay
Delay
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