Ddr3 Dram - Alinx AX7Z035B User Manual

Figure 2-2-3: The XC7Z035 chip used on the Core Board

2.3 DDR3 DRAM

The FPGA board AX7Z035B is equipped with four Micron 512MB DDR3 chips,
model MT41J256M16HA-125 (compatible with MT41K256M16HA-125), each side
has 2 DDR3s mounted. Two DDR3 SDRAMs form a 32-bit bus width. The PS-side
DDR3 SDRAM has a maximum operating speed of 533MHz (data rate 1066Mbps),
and two DDR3 memory systems are directly connected to the memory interface of
the ZYNQ PS BANK 502. The PL-side DDR3 SDRAM has a maximum operating speed
of 800MHz (data rate 1600Mbps), and two DDR3 memory systems are connected to
the BANK33 and BANK34 interfaces of the FPGA. The specific configuration of DDR3
SDRAM is shown in Table 2-3-1.
Bit Number
U4, U5, U7, U8
The hardware design of DDR3 requires strict consideration of signal integrity.
We have fully considered the matching resistor/terminal resistance, line impedance
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Table 2-3-1 DDR3 SDRAM Configuration
Model
MT41J256M16HA-125
AX7Z035B User Manual
Capacity Manufacturer
256M x 16bit Micron
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