Pcie Slot - Alinx AX7Z035B User Manual

AX7Z035B User Manual
SFP3_TX_N
BANK111_TX2_N
SFP3_RX_P
BANK111_RX2_P
SFP3_RX_N
BANK111_RX2_N
SFP4_TX_P
BANK111_TX3_P
SFP4_TX_N
BANK111_TX3_N
SFP4_RX_P
BANK111_RX3_P
SFP4_RX_N
BANK111_RX3_N
SFP12_TX_DIS
SFP34_TX_DIS

3.8 PCIe Slot

The AX7Z035B carrier board has a PCIe x4 interface. In order to be compatible
with the AC7Z100 core board, the PCB is physically made into a PCIE x8 interface. In
the electrical connection, we only have 4 pairs of transceivers connected to the
PCIEx8 slot, so only PCIEex4, PCIex2, PCIex1 data communication can be realized.
The transmit and receive signals of the PCIe interface are directly connected to
the GTX transceiver of the ZYNQ BANK112. Four-channel TX signals and the RX
signals are connected to the BANK112 in differential signal mode, and the single-
channel communication rate can up to 5G bit bandwidth.
The PCIe interface design diagram of the FPGA development board is shown in
Figure 3-8-1, where the TX transmission signal is connected in AC coupling mode.
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B12_L18_N
B12_L18_P
Optical module 3 transmit data
AE1
Optical module 3 receive data
AC6
Optical module 3 receive data
AC5
Optical module 4 transmit data
AC2
Optical module 4 transmit data
AC1
Optical module 4 receive data
AD4
Optical module 4 receive data
AD3
Optical module 12 Light emission
AF17
prohibited, high effective
Optical module 34 Light emission
AE17
prohibited, high effective
positive
negative
positive
negative
positive
negative
positive
negative
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