Alinx AX7Z035B User Manual page 22

AX7Z035B User Manual
PL clock pin assignment:
Signal Name
SYS_CLK_P
SYS_CLK_N
GTX reference clock
The FPGA core board provides a 125Mhz reference clock for the GTX
transceiver. The reference clock is connected to the reference clock input
REFCLK1P/REFCLK1N of the BANK111. The schematic diagram of the clock source is
shown in Figure 2-6-4:
Figure 2-6-5: Programmable clock source on the board
GTX clock source ZYNQ pin assignment:
Signal Name
BANK111_CLK1_P
BANK111_CLK1_N
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Figure 2-6-4: GTX clock source
ZYNQ Pin
C8
C7
ZYNQ Pin
AA6
AA5
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