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Alinx Kosmo2 User Manual

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Kosmo2 Development
Platform User Manual
AXK400 development board
Техническая поддержка и поставка
продукции Pangomicro и Alinx
Компания
Микротерра
fpga@microterra.ru

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Summary of Contents for Alinx Kosmo2

  • Page 1 Kosmo2 Development Platform User Manual AXK400 development board Техническая поддержка и поставка продукции Pangomicro и Alinx Компания Микротерра fpga@microterra.ru...
  • Page 2 AXK400 development board user manual Document version control Document Modify content record Version REV1.0 Create a document 2 / 52...
  • Page 3 AXK400 development board user manual Index DOCUMENT VERSION CONTROL 1. DEVELOPMENT BOARD INTRODUCTION 2. K400 CORE BOARD (1) I NTRODUCTION (2) PG2K400 CHIP (3) DDR3 DRAM (4) F LASH MMC F LASH (6) C LOCK ONFIGURATION (7) LED (8) R ESET CIRCUIT (9) P OWER SUPPLY...
  • Page 4 This Kosmo2 FPGA development platform adopts a core board plus expansion board model to facilitate users’ secondary development and utilization of the core board. The core board uses Unisoc’s Kosmo2 SOPC chip PG2K400 solution, which uses ARM+FPGA SOPC technology to integrate...
  • Page 5 AXK400 development board user manual 1. Development Board Introduction Here, a brief function introduction of this AXK400 Kosmo2 development platform is provided. The entire structure of the development board is designed based on our consistent core board + expansion board model. The core board and the expansion board are connected using high- speed inter-board connectors.
  • Page 6 AXK400 development board user manual Through this schematic diagram, we can see the interfaces and functions that our development platform contains. • PG2K400 core board It is composed of PG2K400+2GB DDR3+8GB eMMC FLASH +256Mb OSPI FLASH. There are also three crystal oscillators to provide clocks, a single-ended 33.3333MHz crystal oscillator is provided to the PU system, a differential 200MHz crystal oscillator is provided to the PA logic DDR reference clock, and another differential 125MHz crystal oscillator Provides reference clock to HSST transceiver.
  • Page 7 AXK400 development board user manual • Micro SD card holder 1x Micro SD card holder, used to store operating system images and file systems. • 40 -pin expansion port 1x 40-pin 2.54mm pitch expansion port, which can be connected to various modules of Black Gold (binocular camera, TFT LCD screen, high-speed AD module, etc.
  • Page 8 K400 (core board model, the same below) core board, PG2K400 chip is based on PG2K400- 6IFFBG676 of Unisoc’s Kosmo2 series. PG2K400 is a SOPC that integrates a dual-core processor (PU) based on ARM® Cortex™-A53MPCore™ and a PANGO programmable logic device (PA) in a single chip.
  • Page 9 Back view of K400 core board (2) PG2K400 chip The core board uses Unisoc's Kosmo2 series chip, model PG2K4006IFFBG676. The chip's PU system integrates two ARM Cortex™-A53 processors, AMBA® interconnect, internal memory, external memory interfaces and peripherals. These peripherals mainly include USB bus interface, Ethernet interface, SD/SDIO interface, I2C bus interface, CAN bus interface, UART interface, GPIO, etc.
  • Page 10 AXK400 development board user manual Figure 2-2-1 Overall block diagram of PG2K400 chip The main parameters of the PU system part are as follows: - Application processor based on ARM dual-core CortexA53, ARM-v8 architecture up to 1GHz - NEON media processing engine - 32KB level 1 instruction and data cache per CPU, 512KB level 2 cache shared between 2 CPUs - On-chip boot ROM and 256KB on-chip RAM - Static memory interface, supports 256KB SRAM, supports NOR Flash, supports ONFI 1.0 NAND...
  • Page 11 AXK400 development board user manual - 2 AD converters that can measure on-chip voltage, temperature sensing and up to 17 external differential input channels, 1MBPS (3) DDR3 DRAM The K400 core board is equipped with four 512MB DDR3 chips, model A3T4GF40BBF-HPI, of which two are mounted on the PU and PA ends.
  • Page 12 AXK400 development board user manual Figure 2-3-2 PA DDR3 DRAM schematic diagram PU-side DDR3 DRAM Pinout: Signal name PG2K400 Pin Number PU_DDR3_DQS0_P PU_DDR3_DQS0_N PU_DDR3_DQS1_P PU_DDR3_DQS1_N PU_DDR3_DQS2_P PU_DDR3_DQS2_N PU_DDR3_DQS3_P PU_DDR3_DQS4_N PU_DDR3_D0 PU_DDR3_D1 PU_DDR3_D2 PU_DDR3_D3 PU_DDR3_D4 PU_DDR3_D5 PU_DDR3_D6 PU_DDR3_D7 PU_DDR3_D8 PU_DDR3_D9 PU_DDR3_D10 PU_DDR3_D11 PU_DDR3_D12 12 / 52...
  • Page 13 AXK400 development board user manual PU_DDR3_D13 PU_DDR3_D14 PU_DDR3_D15 PU_DDR3_D16 PU_DDR3_D17 PU_DDR3_D18 PU_DDR3_D19 PU_DDR3_D20 PU_DDR3_D21 PU_DDR3_D22 PU_DDR3_D23 PU_DDR3_D24 PU_DDR3_D25 PU_DDR3_D26 PU_DDR3_D27 PU_DDR3_D28 PU_DDR3_D29 PU_DDR3_D30 PU_DDR3_D31 PU_DDR3_DM0 PU_DDR3_DM1 PU_DDR3_DM2 PU_DDR3_DM3 PU_DDR3_A0 PU_DDR3_A1 PU_DDR3_A2 PU_DDR3_A3 PU_DDR3_A4 PU_DDR3_A5 PU_DDR3_A6 PU_DDR3_A7 PU_DDR3_A8 PU_DDR3_A9 PU_DDR3_A10 13 / 52...
  • Page 14 AXK400 development board user manual PU_DDR3_A11 PU_DDR3_A12 PU_DDR3_A13 PU_DDR3_A14 PU_DDR3_BA0 PU_DDR3_BA1 PU_DDR3_BA2 PU_DDR3_S0 PU_DDR3_RAS PU_DDR3_CAS PU_DDR3_WE PU_DDR3_ODT PU_DDR3_RESET PU_DDR3_CLK0_P PU_DDR3_CLK0_N PU_DDR3_CKE PA DDR3 DRAM Pinout: Signal name PG2K400 Pin Number PA_DDR3_DQS0_P PA_DDR3_DQS0_N PA_DDR3_DQS1_P PA_DDR3_DQS1_N PA_DDR3_DQS2_P PA_DDR3_DQS2_N PA_DDR3_DQS3_P PA_DDR3_DQS4_N PA_DDR3_D0 PA_DDR3_D1 PA_DDR3_D2 PA_DDR3_D3 PA_DDR3_D4...
  • Page 15 AXK400 development board user manual PA_DDR3_D6 PA_DDR3_D7 PA_DDR3_D8 PA_DDR3_D9 PA_DDR3_D10 PA_DDR3_D11 PA_DDR3_D12 PA_DDR3_D13 PA_DDR3_D14 PA_DDR3_D15 PA_DDR3_D16 PA_DDR3_D17 PA_DDR3_D18 PA_DDR3_D19 PA_DDR3_D20 PA_DDR3_D21 PA_DDR3_D22 PA_DDR3_D23 PA_DDR3_D24 PA_DDR3_D25 PA_DDR3_D26 PA_DDR3_D27 PA_DDR3_D28 PA_DDR3_D29 PA_DDR3_D30 PA_DDR3_D31 PA_DDR3_DM0 PA_DDR3_DM1 PA_DDR3_DM2 PA_DDR3_DM3 PA_DDR3_A0 PA_DDR3_A1 PA_DDR3_A2 PA_DDR3_A3 15 / 52...
  • Page 16 AXK400 development board user manual PA_DDR3_A4 PA_DDR3_A5 PA_DDR3_A6 PA_DDR3_A7 PA_DDR3_A8 PA_DDR3_A9 PA_DDR3_A10 PA_DDR3_A11 PA_DDR3_A12 PA_DDR3_A13 PA_DDR3_A14 PA_DDR3_BA0 PA_DDR3_BA1 PA_DDR3_BA2 PA_DDR3_S0 PA_DDR3_RAS PA_DDR3_CAS PA_DDR3_WE PA_DDR3_ODT PA_DDR3_RESET PA_DDR3_CLK0_P PA_DDR3_CLK0_N PA_DDR3_CKE (4) Flash The core board is equipped with 2 pieces of flash, one is a 128MBit Quad-SPI FLASH chip, and the other is an 8-bit 256Mbits OSPI FLASH, which uses the 3.3V CMOS voltage standard.
  • Page 17 AXK400 development board user manual QSPI FLASH is connected to the GPIO port of BANKL0 of the PU part of the PG2K400 chip. In system design, the GPIO port function of these PU ends needs to be configured as OSPI. FLASH interface.

  • Page 18: Clock Configuration

    AXK400 development board user manual Position No. Chip Type capacity FEMDRW008G-88A39 8G Byte Table 2-5-1 eMMC Flash model and parameters eMMC FLASH is connected to the GPIO port of BANKL1 of the PU part of the PG2K400 chip. In the system design, the GPIO port functions of these PU sides need to be configured as SD interfaces. Figure 2-5-1 is the part of eMMC Flash in the schematic diagram.
  • Page 19 AXK400 development board user manual Figure 2-6-1 Core board clock source PU system clock source The PG2K400 chip provides a 33.333MHz clock input to the PU part through the X4 crystal oscillator on the core board. The clock input is connected to the PU_CLK_500 pin of BANKL0 of the PG2K400 chip.
  • Page 20 AXK400 development board user manual Figure 2-6-4 PA system clock source PA clock pin assignment: Signal name PG2K400 Pinout SYS_CLK_P SYS_CLK_N HSSTHP reference clock The core board provides a 125Mhz reference clock for the HSSTHP transceiver. The reference clock is connected to the reference clock input REFCLK1P/REFCLK1N of BANKQR8. The schematic diagram of this clock source is shown in Figure 2-6-6 Figure 2-6-6 HSSTHP clock source 20 / 52...
  • Page 21 AXK400 development board user manual Figure 6-7 is a physical picture of the HSSTHP clock source Figure 2-6-7 Actual picture of programmable clock source HSSTHP clock source PG2K400 pin assignment: Signal name PG2K400 Pinout BANKQR8_CLK1_P BANKQR8_CLK1_N (7) LEDs There are 3 red LED lights on the K400 core board, 1 of which is the power indicator light (PWR), 1 is the configuration LED light (DONE), and 1 is the user LED light.

  • Page 22: Reset Circuit

    AXK400 development board user manual LED Light PG2K400 Pin Name PG2K400 Pin Remark Number L6_IO25 User LED Light (8) Reset circuit There is a reset circuit on the K400 core board. The reset input signal is connected to the reset button on the bottom board, and the reset output is connected to the PG2K400 chip PU reset pin.
  • Page 23 AXK400 development board user manual Figure 2-9-1 Power supply interface part in the schematic diagram 23 / 52...
  • Page 24 AXK400 development board user manual +5V generates +1.0V PG2K400 core power supply through the DCDC power chip IS6608A. The +1.0V power supply output current is as high as 30A, which far meets the current demand of the PG2K400 core voltage. The +5V power supply is then generated by the DCDC chip ETA1471 to generate HSST_AVTT, +1.5V, +3.3V, and +1.5V four-way power supplies.

  • Page 25: Structure Diagram

    AXK400 development board user manual (10) Structure diagram Top View (11) Connector pin definition The core board has a total of 4 high-speed expansion ports, which are connected to the baseboard using 4 120-pin inter-board connectors (J29~J32). Among them, J29 is connected to the IO of BANKL7 and BANKL6, J30 is connected to the transceiver signal of HSSTHP, J31 is connected to the IO of JTAG and BANKR4 (1.8V level...
  • Page 26 AXK400 development board user manual L6_L15_P AF19 L6_L14_P AC21 L6_L23_N L6_L7_P AE22 L6_L23_P L6_L7_N AF22 L6_L22_P AA19 L6_L20_P AA20 L6_L22_N AB19 L6_L20_N AB20 L6_L17_N AD19 L6_L18_N AF18 L6_L17_P AD18 L6_L18_P AE18 L6_L19_N L6_L16_N AE21 L6_L19_P L6_L16_P AE20 L6_L24_N AA18 L6_L21_N AC19 L6_L24_P L6_L21_P...
  • Page 27 AXK400 development board user manual L7_L7_N AD10 L7_L8_P AE12 L7_L24_P L7_L21_P AC17 L7_L24_N L7_L21_N AC16 L7_L3_N AA10 L7_L17_P AE16 L7_L3_P L7_L17_N AE15 L7_L11_P AC12 L7_L22_P AA15 L7_L11_N AD11 L7_L22_N AA14 L7_L12_N AD13 L7_L5_P L7_L12_P AC13 L7_L5_N L7_L6_P AA13 L7_L9_P AE11 L7_L6_N AA12 L7_L9_N...
  • Page 28 AXK400 development board user manual BANKQR7_TX0_N BANKQR7_RX0_N BANKQR7_TX0_P BANKQR7_RX0_P BANKQR7_TX1_N BANKQR7_RX1_N BANKQR7_TX1_P BANKQR7_RX1_P BANKQR7_TX2_N BANKQR7_RX2_N BANKQR7_TX2_P BANKQR7_RX2_P BANKQR7_TX3_N BANKQR7_RX3_N BANKQR7_TX3_P BANKQR7_RX3_P BANKQR7_CLK0_N BANKQR7_CLK1_N BANKQR7_CLK0_P BANKQR7_CLK1_P BANKQR8_RX3_N BANKQR8_RX3_P BANKQR8_TX3_N BANKQR8_TX3_P BANKQR8_RX2_N BANKQR8_RX2_P BANKQR8_TX2_N BANKQR8_TX2_P BANKQR8_RX1_N 28 / 52...
  • Page 29 AXK400 development board user manual BANKQR8_RX1_P BANKQR8_TX1_N BANKQR8_TX1_P BANKQR8_RX0_N BANKQR8_RX0_P BANKQR8_TX0_N BANKQR8_TX0_P BANKQR8_CLK0_N BANKQR8_CLK0_P J31 connector PG2K400 PG2K400 J31 Pin Signal name J31 Pin Signal name Pin Number Pin Number FPGA_TCK FPGA_TDI FPGA_TMS FPGA_TDO R4_L3_P R4_L2_P R4_L3_N R4_L2_N R4_L7_N R4_L6_P R4_L7_P R4_L6_N R4_L4_P...
  • Page 30 AXK400 development board user manual R4_L5_N R4_L22_P R4_L5_P R4_L22_N R4_L8_P R4_L24_N R4_L8_N R4_L24_P R4_L12_P R4_L11_N R4_L12_N R4_L11_P R4_L9_P R4_L19_N R4_L9_N R4_L19_P R4_L1_N R4_L21_N R4_L1_P R4_L21_P R4_L17_N R4_L14_P R4_L17_P R4_L14_N R4_L20_N R4_L18_P R4_L20_P R4_L18_N R4_L10_N R4_L15_N R4_L10_P R4_L15_P R4_L13_N R4_L13_P R4_L16_N R4_L16_P 30 / 52...
  • Page 31 AXK400 development board user manual PU_POR_B SYS_RESET J32 Connector J32 Pinout Signal name J32 Pinout Signal name PG2K400 PG2K400 Pin Number Pin Number PU_MIO5 PU_MIO17 PU_MIO4 PU_MIO18 PU_MIO14 PU_MIO19 PU_MIO15 PU_MIO20 PU_MIO52 PU_MIO16 PU_MIO53 PU_MIO21 PU_MIO7 PU_MIO26 PU_MIO25 PU_MIO40 PU_MIO24 PU_MIO41 PU_MIO23 31 / 52...
  • Page 32 AXK400 development board user manual PU_MIO42 PU_MIO27 PU_MIO43 PU_MIO22 PU_MIO44 PU_MIO30 PU_MIO45 PU_MIO29 PU_MIO36 PU_MIO31 PU_MIO32 PU_MIO33 PU_MIO34 PU_MIO35 PU_MIO28 PU_MIO37 PU_MIO38 PU_MIO39 L6_L1_P AA25 L6_L11_P AD23 L6_L1_N AB25 L6_L11_N AD24 L6_L6_P AA24 L6_L4_P AD25 L6_L6_N AB24 L6_L4_N AD26 L6_L2_N AC26 L6_L5_P AF24...
  • Page 33 AXK400 development board user manual L6_L2_P AB26 L6_L5_N AF25 L6_L12_P AC23 L6_L3_P AE25 L6_L12_N AC24 L6_L3_N AE26 33 / 52...

  • Page 34: Expansion Board

    AXK400 development board user manual 3. Expansion Board (1) Introduction Through the previous function introduction, we can understand the functions of the expansion board ⚫ 1x PCIEx4 interface ⚫ 4 -way fiber optic interface ⚫ 2x 10 /100M/1000M Ethernet RJ-45 ports ⚫...

  • Page 35: Gigabit Ethernet Interface

    PA side is connected to the IO of BANK R4. The YT8531H chip supports 10/100/1000Mbps network transmission rate and communicates data with the MAC layer of the Kosmo2 system through the RGMII interface. YT8531HD supports MDI/MDX adaptation, various speed adaptation, Master/Slave adaptation, and supports MDIO bus for PHY register management.
  • Page 36 AXK400 development board user manual RXD1_TXDLY TX clock 2ns delay Delay RXD0_RXDLY RX clock 2ns delay Delay Table 3-3-1 PHY chip default configuration values When the network is connected to Gigabit Ethernet, the data transmission of PG2K400 and PHY chip YT8531H is communicated through the RGMII bus. The transmission clock is 125Mhz, and the data is sampled on the rising edge and falling edge of the clock.
  • Page 37 AXK400 development board user manual Figure 3-3-2 PG2K400 PA terminal and GPHY connection diagram The PU-side Gigabit Ethernet pin assignment is as follows: Signal name PG2K400 Pin Name PG2K400 Pin Number Remark PHY1_TXCK PU_MIO16_L1 RGMII Transmit Clock PHY1_TXD0 PU_MIO17_L1 Send data bit 0 PHY1_TXD1 PU_MIO18_L1 Send data bit1...
  • Page 38 AXK400 development board user manual The Gigabit Ethernet pin assignments on the PA side are as follows: Signal name PG2K400 Pin Name PG2K400 Pin Number Remark PHY2_TXCK R4_L23_P RGMII Transmit Clock PHY2_TXD0 R4_L2_P Send data bit 0 PHY2_TXD1 R4_L2_N Send data bit1 PHY2_TXD2 R4_L6_P Send data bit2...
  • Page 39 Among them, the video digital interface, audio digital interface and I2C configuration interface of ADV7511 are connected to the BANKR4 IO of the Kosmo2PU part. The Kosmo2 system initializes and controls the ADV7511 through the I2C pins. The hardware connection diagram between the...
  • Page 40 AXK400 development board user manual Figure 3-5-1 HDMI output interface design schematic Pinout of PG2K400 : Signal name PG2K400 Pin name PG2K400 Pin number Remark HDMI_CLK R4_L9_P HDMI video signal clock HDMI_HSYNC R4_L3_N HDMI video signal horizontal synchronization HDMI_VSYNC R4_L3_P HDMI video signal column synchronization HDMI_DE...
  • Page 41 AXK400 development board user manual HDMI_D13 R4_L17_P HDMI video signal data 13 HDMI_D14 R4_L20_N HDMI video signal data 14 HDMI_D15 R4_L20_P HDMI video signal data 15 HDMI_D16 R4_L10_N HDMI video signal data 16 HDMI_D17 R4_L10_P HDMI video signal data 17 HDMI_D18 R4_L13_N HDMI video signal data 18...
  • Page 42 AXK400 development board user manual Pinout of PG2K400 : Signal name Remark PG2K400 Pin name PG2K400 Pin number 9013_nRESET L6_L24_N AA18 9013 reset signal 9013_CLK L6_L11_P AD23 9013 Video signal clock 9013_HS L6_L5_P AF24 9013 video signal line synchronization 9013_VS L6_L5_N AF25 9013 Video signal column...

  • Page 43: Fiber Optic Interface

    AXK400 development board user manual 9013 _SDA L6_L3_P AE25 9013 IIC Control Data (7) Fiber Optic Interface The AXK400 expansion board has 4 optical fiber interfaces. Users can purchase SFP optical modules (1.25G, 2.5G, 10G optical modules on the market) and insert them into these 4 optical fiber interfaces for optical fiber data communication.

  • Page 44: Pcie Slots

    AXK400 development board user manual Positive SFP2_TX_N BANKQR8_TX1_N Optical Module 2 Data Transmission Negative SFP2_RX_P BANKQR8_RX1_P Optical module 2 Data reception positive SFP2_RX_N BANKQR8_RX1_N Optical module 2 Data reception negative SFP3_TX_P BANKQR8_TX2_P Optical Module 3 Data Transmission Positive SFP3_TX_N BANKQR8_TX2_N Optical Module 3 Data Transmission Negative SFP3_RX_P...
  • Page 45 AXK400 development board user manual in which the TX transmission signal is connected in AC coupling mode. Figure 3-8-1 PCIe slot design diagram PCIe x4 interface PG2K400 pin assignment is as follows: Signal name PG2K400 Pin Remark PG2K400 Name Pin number PCIE_RX0_P BANKQR7_RX3_P PCIE channel 0 data receiving positive...

  • Page 46: Sd Card Slot

    AXK400 development board user manual PCIE_PERST L6_L24_P Reset signal of PCIE board (9) SD Card slot The AXK400 baseboard contains a Micro SD card interface to provide users with access to SD card memory, which is used to store the BOOT program of the PG2K400 chip, the Linux operating system kernel, the file system and other user data files.
  • Page 47 34 channels. The IO of the PG2K400 chip BANKL7 connected to the IO of the expansion port defaults to 3.3V. Do not directly connect it to external 5V devices to avoid burning out the Kosmo2 chip. If you want to connect a 5V device, you need to connect a level conversion chip.
  • Page 48 AXK400 development board user manual IO1_14N AE12 IO1_14P AF12 IO1_15N AB10 IO1_15P AB11 IO1_16N AB16 IO1_16P AB17 IO1_17N AA17 IO1_17P +3.3V +3.3V (11) LED lamp There are 7 light-emitting diode LEDs, 1 power indicator light, 2 serial communication indicator lights, and 4 PA control indicator lights on the AXK400 base plate. When the development board is powered on, the power indicator light will light up;...
  • Page 49 AXK400 development board user manual Pin assignment of user LEDs Signal name PG2K400 Pin Name PG2K400 Pin Remark Number PL_LED1 L7_L14_P AB15 User PL LED1 PL_LED2 L7_L14_N AB14 User PL LED2 PL_LED3 L7_L10_N AF13 User PL LED3 PL_LED4 L7_L10_P AE13 User PL LED4 (12) Reset button and user button There is 1 reset button RESET and 4 user buttons on the AXK400 base plate.

  • Page 50: Jtag Debug Port

    AXK400 development board user manual (13) JTAG Debug port A JTAG interface is reserved on the AXK400 base board for downloading PG2K400 programs or firmware programs to FLASH. In order to prevent damage to the PG2K400 chip caused by hot plugging and unplugging, we added a protection diode to the JTAG signal to ensure that the signal voltage is within the acceptable range of the FPGA and avoid damage to the PG2K400 chip.

  • Page 51: Power Supply

    AXK400 development board user manual OFF, OFF 1. 1 SD Card OFF、 ON 1, 0 QSPI FLASH Table 3-14-1 SW1 boot mode configuration (15) Power supply The power input voltage of the development board is DC12V, and the board can be powered through the PCIE slot or an external +12V power supply.
  • Page 52 AXK400 development board user manual and fan to the chip on the board to prevent the chip from overheating. The fan is controlled by the PG2K400 chip. The control pin is connected to the IO of BANKL7. If the IO level output is low, the MOSFET tube is turned on and the fan works.

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