Part 5: Clock Configuration; Part 5.1: Ps System Clock Source - Alinx ZYNQ 7000 User Manual

After the ZYNQ702 chip is powered up, it will detect the level of the responding
MIO port to determine which startup mode. Users can select different startup
modes through the J13 jumper on the FPGA development board. The J13
startup mode configuration is shown in Table 4-1.

Part 5: Clock Configuration

The AX7020 FPGA development board provides active clocks for the PS
system and the PL logic, respectively. The PS system and PL logic can work
independently.

Part 5.1: PS system clock source

The ZYNQ chip provides a 33.333MHz clock input to the PS section via
the X1 crystal on the development board. The input of the clock is connected to
the pin of the PS_CLK_500 of the BANK500 of the ZYNQ chip. The schematic
diagram is shown in Figure 5-1:
Figure 5-1: Active crystal oscillator to the PS section
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ZYNQ FPGA Development Board AX7020 User Manual
J13
Connect the left two pins
Connect the middle two pins
Two pins connected to the right
Table 4-1: startup mode configuration
Jump cap position Start mode
SD Card
QSPI FLASH
JTAG