Usb2.0 Host Interface - Alinx AX7Z035B User Manual

PHY2_RXD1
PHY2_RXD2
PHY2_RXD3
PHY2_RXCTL
PHY2_MDC
PHY2_MDIO
PHY2_RESET

3.4 USB2.0 Host Interface

There are 4 USB2.0 HOST interfaces on the AX7Z035B FPGA development board.
The USB2.0 transceiver uses a 1.8V, high-speed USB3320C-EZK chip that supports
the ULPI standard interface, and then expands the 4-way USB HOST interfaces
through a USB HUB chip USB2514. ZYNQ's USB bus interface is connected to the
USB3320C-EZK transceiver for data communication in the high-speed USB2.0 Host
mode. The USB3320C's USB data and control signals are connected to the IO port of
PS BANK501 of the ZYNQ chip. The USB interface's differential signal (DP/DM) is
connected to the USB2514 chip to extend four USB interfaces. Two 24MHz crystals
provide clocks for USB3320C and USB2514 chips, respectively.
Four USB interfaces are flat-type USB interfaces (USB Type A), which allows users
to connect different USB Slave peripherals (such as USB mouse and USB keyboard)
at the same time. Each USB interface provides +5V power.
The schematic diagram of the connection among ZYNQ processor, USB3320C-
EZK chip and USB2514 chip is shown as Figure 3-4-1:
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B35_L24_N
B35_L22_N
B35_L22_P
B35_L11_N
B35_L19_N
B35_L19_P
B35_L21_N
AX7Z035B User Manual
A12 Receive data Bit1
B12 Receive data Bit2
C12 Receive data Bit3
Receive data valid
F14
MDIO Management
C13
MDIO Management
D13
A14
signal
clock
data
Reset signal
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