Alinx AX7Z035B User Manual page 21

AX7Z035B User Manual
Figure 2-6-2: PS active crystal oscillator
Clock pin assignment:
Signal Name ZYNQ Pin
PS_CLK B24
PL system clock source
The board has a differential 200MHz PL system clock source for the reference
clock of the DDR3 controller. The crystal output is connected to the MRCC of the
FPGA BANK34, which can be used to drive the DDR3 controller and user logic in the
FPGA. The schematic diagram of the clock source is shown in Figure 2-6-3:
Figure 2-6-3: PL system clock source
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