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Alinx AXP100 Instruction Manual

Logos-2 fpga development platform
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Logos-2 series
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Summary of Contents for Alinx AXP100

  • Page 1 Logos-2 series FPGA development platform AXP100...
  • Page 2 Document versioning Document Modify content records version REV1.0 Create documentation www.alinx.com 2 / 52 https://innek.ru/...

  • Page 3: Table Of Contents

    AXP100 User Manual Table of contents 1, Introduction to Development Board ..............5 2 FPGA Core board ...................... 8 ( 1 ) Introduction ....................8 (2 ) FPGA ......................... 9 (3 ) Active crystal oscillator ................. 10 (4 ) DDR3 ......................13 (5 ) QSPI Flash .....................
  • Page 4 FPGA development platform (model: AXP100) based Ziguang Tongchuang Logos-2 series has been officially released. In order to give you a quick understanding of this development platform, we have written this user manual. This Logos2 FPGA development platform adopts the idea of core board plus expansion board, which is convenient for users to develop and utilize the core board for the second time .

  • Page 5: 1, Introduction To Development Board

    AXP100 User Manual 1. Introduction to the development board Here, a simple function introduction to this AXP100 FPGA development platform. The entire structure of the development board is designed by inheriting our usual core board + expansion board model. High-speed inter-board connectors are used to connect the core board and the expansion board.
  • Page 6 One 10/100M/1000M Ethernet RJ-45 interface ⚫ The Gigabit Ethernet interface chip adopts KSZ9031RNX Ethernet PHY chip to provide users with network communication services. KSZ9031RNX chip supports 10/100/1000 Mbps network transfer rate; full duplex and adaptive. www.alinx.com 6 / 52 https://innek.ru/...
  • Page 7 AXP100 User Manual ⚫ One HDMI output We chose Silicon Image 's SIL9134 HDMI encoding chip, supports up to 1080P@60Hz output, and supports 3D output. ⚫ One HDMI input We chose Silicon Image 's SIL9011/SIL9013 HDMI decoding chip, supports up to 1080P@60Hz input, and supports data output in different formats.

  • Page 8: Fpga Core Board

    ADC module inside the FPGA is led out, and the size of the core board is only 60*60 (mm), which is very suitable for secondary development. Front view of P100 core board www.alinx.com 8 / 52 https://innek.ru/...

  • Page 9: 2 ) Fpga

    AXP100 User Manual Back view of P100 core board ( 2 ) FPGA As mentioned earlier, the FPGA model we use is PG2L100H-6IFBG676, which belongs to the Logos2 family, with a speed grade of 6 and an industrial temperature grade. This model is packaged in FBG676 with 676 pins. The chip naming rules of Logos2 FPGA are as follows: Figure 2-2-1 is the physical diagram of the FPGA chip used in the development board.

  • Page 10: 3 ) Active Crystal Oscillator

    V is the power HSSTAVCC supply voltage of the HSSTLP transceiver inside the FPGA, connected to 1.0V, is the termination voltage of the HSSTLP transceiver, connected to 1.2V. HSSTAVCCPLL ( 3 ) Active crystal oscillator www.alinx.com 10 / 52 https://innek.ru/...
  • Page 11 AXP100 User Manual The P100 core board is equipped with 3 active differential crystal oscillators from Sitime Company, one is 200MHz, the model is SiT9121-200.00MHz , used for the system main clock of FPGA and used to generate DDR3 control clock; the other two are 125MHz, the model is SiT9121-125MHz, used for the reference clock input of HSSTLP transceiver.
  • Page 12 Figure 2-3-3 125Mhz Active Differential Crystal Oscillator Figure 2-3-4 125M active crystal oscillator photo www.alinx.com 12 / 52 https://innek.ru/...

  • Page 13: 4 ) Ddr3

    AXP100 User Manual Clock pin assignment: pin name FPGA pins Q3_REFCKP Q3_REFCKN Q6_REFCKP AA11 Q6_REFCKN AB11 3). 50Mhz active crystal oscillator Y1 in Figure 2-3-5 is the 50M active crystal oscillator circuit. This clock is connected to the global clock pin inside the FPGA , which can be the reference input clock provided by the FPGA, using Sitime's SiT8008-50.
  • Page 14 DDR3 Data high 16 bits BANK FPGA R4/R5 address line, control line DDR3 Data lower 16 bits Figure 2-4-1 DDR3 Schematic diagram of DRAM schematic Figure 2-4-2 DDR3 DRAM physical map DDR3 DRAM pin assignment: www.alinx.com 14 / 52 https://innek.ru/...
  • Page 15 AXP100 User Manual Signal name FPGA pin name DDR3_DQS3_P DDR3_DQS3_N DDR3_DQS2_P DDR3_DQS2_N DDR3_DQS1_P DDR3_DQS1_N DDR3_DQS0_P DDR3_DQS0_N DDR3_DM3 DDR3_DM2 DDR3_DM1 DDR3_DM0 DDR3_D31 DDR3_D30 DDR3_D29 DDR3_D28 DDR3_D27 DDR3_D26 DDR3_D25 DDR3_D24 DDR3_D23 DDR3_D22 DDR3_D21 DDR3_D20 DDR3_D19 DDR3_D18 DDR3_D17 DDR3_D16 DDR3_D15 DDR3_D14 DDR3_D13 www.alinx.com 15 / 52 https://innek.ru/...
  • Page 16 DDR3_D12 DDR3_D11 DDR3_D10 DDR3_D9 DDR3_D8 DDR3_D7 DDR3_D6 DDR3_D5 DDR3_D4 DDR3_D3 DDR3_D2 DDR3_D1 DDR3_D0 DDR3_A14 DDR3_A13 DDR3_A12 DDR3_A11 DDR3_A10 DDR3_A9 DDR3_A8 DDR3_A7 DDR3_A6 DDR3_A5 DDR3_A4 DDR3_A3 DDR3_A2 DDR3_A1 DDR3_A0 DDR3_BA2 DDR3_BA1 DDR3_BA0 DDR3_WE www.alinx.com 16 / 52 https://innek.ru/...

  • Page 17: 5 ) Qspi Flash

    AXP100 User Manual DDR3_S0 DDR3_RESET DDR3_RAS DDR3_ODT DDR3_CLK0_P DDR3_CLK0_N DDR3_CKE0 DDR3_CAS ( 5 ) QSPI Flash The core board uses two 128Mbit QSPI FLASH chips, the model is GD25Q127CYIG, which uses the 3.3V CMOS voltage standard. Due to its non- volatile characteristics, in use, QSPI FLASH can be used as the boot image of the FPGA system.

  • Page 18: (6 ) Led Lamp

    When the IO voltage connected to the user LED light is high, the user LED light is on, and when the connected IO voltage is low, the user LED light will be on. is extinguished. The schematic diagram of LED light hardware connection is shown in Figure 2-6-1: www.alinx.com 18 / 52 https://innek.ru/...
  • Page 19 AXP100 User Manual Figure 2-6-1 Schematic diagram of LED connection Figure 2-6-2 is the physical picture of the LED lights on the core board Figure 2-6-2 Physical map of LED lights on the core board Pin assignments for user LEDs...

  • Page 20: 7 ) Expansion Interface

    VCCIN PIN5 VCCIN PIN6 VCCIN PIN7 VCCIN PIN8 VCCIN PIN9 PIN10 PIN11 PIN12 L6_L19_P 3.3V PIN13 L6_L15_N 3.3V PIN14 L6_L19_N 3.3V PIN15 L6_L17_P 3.3V PIN16 L6_L18_P 3.3V PIN17 L6_L17_N 3.3V PIN18 L6_L18_N 3.3V PIN19 PIN20 www.alinx.com 20 / 52 https://innek.ru/...
  • Page 21 AXP100 User Manual PIN21 L6_L23_P 3.3V PIN22 L6_L22_P 3.3V PIN23 L6_L23_N 3.3V PIN24 L6_L22_N 3.3V PIN25 L6_L20_P 3.3V PIN26 L6_L12_P 3.3V PIN27 L6_L20_N 3.3V PIN28 L6_L12_N 3.3V PIN29 PIN30 PIN31 L6_L24_P 3.3V PIN32 L6_L16_P 3.3V PIN33 L6_L24_N 3.3V PIN34 L6_L16_N 3.3V...
  • Page 22 3.3V PIN47 L5_L14_P 3.3V PIN48 L5_L16_N 3.3V PIN49 PIN50 PIN51 L5_L19_N 3.3V PIN52 L5_L10_N 3.3V PIN53 L5_L19_P 3.3V PIN54 L5_L10_P 3.3V PIN55 L5_L17_N 3.3V PIN56 L5_L13_N 3.3V PIN57 L5_L17_P 3.3V PIN58 L5_L13_P 3.3V PIN59 PIN60 www.alinx.com 22 / 52 https://innek.ru/...
  • Page 23 AXP100 User Manual PIN61 L6_L6_P 3.3V PIN62 L5_L3_N 3.3V PIN63 L6_L6_N 3.3V PIN64 L5_L3_P 3.3V PIN65 L5_L21_N 3.3V PIN66 L6_L7_N AB25 3.3V PIN67 L5_L21_P 3.3V PIN68 L6_L7_P AA24 3.3V PIN69 PIN70 PIN71 L5_L24_P 3.3V PIN72 L6_L11_N 3.3V PIN73 L5_L24_N 3.3V...
  • Page 24 PIN78 FPGA_TDI 3.3V PIN79 FPGA_TDO 3.3V PIN80 FPGA_TMS 3.3V Figure 2-7-3 is the physical diagram of the CON3 expansion port connector, the Pin1 of the connector has been marked with a dot on the board. www.alinx.com 24 / 52 https://innek.ru/...
  • Page 25 AXP100 User Manual Figure 2-7-3 Physical map of CON3 expansion port connector Expansion port CON4 The 80Pin connector CON4 is used to expand the high-speed data and clock signals of the common IO and HSSTLP of BANK L3 and R5 of the FPGA. The voltage standard of the IO port of L3 can be adjusted by modifying the resistance of the power supply resistor.
  • Page 26 Figure 2-7-4 is the physical diagram of the CON4 expansion port connector, the Pin1 of the connector has been marked with a dot on the board. Figure 2-10-4 Physical map of CON4 expansion port connector www.alinx.com 26 / 52 https://innek.ru/...

  • Page 27: (8 ) Power

    AXP100 User Manual ( 8 ) Power supply The power supply voltage of the P100 core board is V , and the input voltage CCIN is 5V, which needs to be powered through the connector CON1, and the power supply through the backplane when connecting to the backplane. The schematic diagram of the power supply design on the board is shown in Figure 2-8-1 below.
  • Page 28 FPGA L3, L6 HSST_VCC12(+1.2V) FPGA HSSTLP transceivers Q3, Q6 HSST_VCC10(+1.0V) FPGA HSSTLP transceivers Q3, Q6 P100 core board is shown in Figure 2-8-2 below. 2-8-2 Physical map of the power supply parts of the core board www.alinx.com 28 / 52 https://innek.ru/...

  • Page 29: (9 ) Junction Diagram

    AXP100 User Manual ( 9 ) Structure diagram Front view (Top View) Rear view (Bottom View) www.alinx.com 29 / 52 https://innek.ru/...

  • Page 30: Expansion Board

    4 user LED lights ⚫ (2 ) Gigabit Ethernet interface The AXP100 development board provides users with network communication services through a KSZ9031RNX Ethernet PHY chip. The Ethernet PHY chip is connected to the IO interface of Logos2 FPGA. KSZ9031RNX chip supports 10/100/1000 Mbps network transmission rate, and communicates with FPGA through RGMII interface .
  • Page 31 AXP100 User Manual When the network is connected to Gigabit Ethernet, the data transmission between the FPGA a n d t h e PHY chip KSZ9031RNX communicates through the RGMII bus, the transmission clock is 125Mhz, and the data is sampled on the rising edge and falling sample of the clock.

  • Page 32: 3 ) Optical Fiber Interface

    ETH_TXD3 (3 ) Optical fiber interface The AXP100 expansion board has 2 optical fiber interfaces. Users can purchase optical modules ( 1.25G, 2.5G optical modules on the market ) and plug them into these two optical fiber interfaces for optical fiber data communication. The 2 optical fiber interfaces are respectively connected with the 2 RX/TX of the HSSTLP transceiver of the FPGA.
  • Page 33 AXP100 User Manual Figure 3-3-2 Photo of optical fiber communication interface The pin assignment of the first optical fiber interface FPGA is as follows: Network name FPGA pins Remark SFP1_TX_P SFP optical module data transmission Positive SFP1_TX_N SFP optical module data transmission Negative...

  • Page 34: 4 ) Pcie X4 Interface

    (4 ) PCIe x4 interface The AXP100 expansion board provides an industrial-grade high-speed data transmission PCIe x2 interface. The size of the PCIE card meets the electrical specifications of the standard PCIe card and can be used directly on the x2 PCIe slot of a common PC.

  • Page 35: 5 ) Hdmi Output Interface

    AXP100 User Manual PCIe The x2 interface FPGA pin assignments are as follows: Network name FPGA pins Remark PCIE_RX0_P PCIE channel 0 data reception Positive PCIE_RX0_N PCIE channel 0 data reception Negative PCIE_RX1_P PCIE channel 1 data reception Positive PCIE_RX1_N...
  • Page 36 Figure 3-5-2 Photo of HDMI interface FPGA pin assignments: Pin name FPGA pins 9134_VS AA24 9134_NRESET 9134_HS AB25 9134_DE 9134_D9 9134_D8 9134_D7 9134_D6 9134_D5 9134_D4 9134_D3 9134_D23 9134_D22 9134_D21 9134_D20 9134_D2 9134_D19 9134_D18 9134_D17 9134_D16 9134_D15 www.alinx.com 36 / 52 https://innek.ru/...

  • Page 37: 6 ) Hdmi Input Interface

    AXP100 User Manual 9134_D14 9134_D13 9134_D12 9134_D11 9134_D10 9134_D1 9134_D0 9134_CLK HDMI_SCL HDMI_SDA (6 ) HDMI input interface Silicon Image SIL9013 HDMI decoding chip is used. It supports up to 1080P@60Hz input and data output in different formats. The SIL9013 is initialized and controlled through the FPGA programming. The hardware connection of the HDMI input interface is shown in Figure 3-6-1.
  • Page 38 Figure 3-6- 2 HDMI Input interface photo FPGA pin assignments: Pin name FPGA pins 9013_VS 9013_NRESET 9013_HS 9013_DE 9013_D9 9013_D8 9013_D7 9013_D6 9013_D5 9013_D4 9013_D3 9013_D23 9013_D22 9013_D21 9013_D20 9013_D2 9013_D19 9013_D18 9013_D17 9013_D16 www.alinx.com 38 / 52 https://innek.ru/...

  • Page 39: 7 ) Sd Card Slot

    AXP100 User Manual 9013_D15 9013_D14 9013_D13 9013_D12 9013_D11 9013_D10 9013_D1 9013_D0 9013_CLK HDMI_SCL HDMI_SDA (7 ) SD card slot SD card (Secure Digital Memory Card) is a memory card based on semiconductor flash memory technology. SD card is a very common storage device now. The SD card we expanded supports SPI mode and SD mode, and the SD card used is MicroSD card.

  • Page 40: 8 ) Usb To Serial Port

    SD_DAT3 (8) USB Convert serial port AXP100 development board contains Silicon Labs CP2102GM USB-UART chip, USB interface adopts miniUSB connector, you can use a USB cable to connect it to the USB port of the PC for serial data communication. The schematic diagram...

  • Page 41: 9 ) Eeprom 24Lc04

    UART1_TXD (9 ) EEPROM 24LC04 AXP100 development board has a 24LC04 EEPROM IC, capacity: 4Kbit (2*256*8bit ) , composed of 2 blocks of 256byte , communicate through the IIC bus . The on-board EEPROM is to learn the communication method of the IIC bus .

  • Page 42: 10 ) Temperature Sensor

    I2C_SCL I2C_SDA (10 ) Temperature sensor AXP100 development board is equipped with a high-precision, low-power, digital temperature sensor chip, model LM75 from ON Semiconductor . The temperature accuracy of the LM75 chip is 0.5 degrees, the sensor and the FPGA are directly connected via I2C digital interface, and the FPGA reads the local temperature through the I2C interface.

  • Page 43: 11) Expansion Port

    AXP100 User Manual 3.3V FPGA Logos2 Figure 3-10-1 The schematic diagram of the LM75 sensor The following picture shows the physical map of the LM75 sensor Figure 3-10-2 LM75 sensor photo LM75 sensor pinout: Pin name FPGA pins I2C_SCL I2C_SDA...
  • Page 44 The picture below is the physical picture of the J4 expansion port. Pin1 and Pin2 of the expansion port have been marked on the board. Figure 3-11-2 Physical map of expansion port J11 Pin assignment of J11 expansion port FPGA Pin number FPGA pins Pin number FPGA pins www.alinx.com 44 / 52 https://innek.ru/...
  • Page 45 AXP100 User Manual +3.3V +3.3V expansion port (J13 ) is shown in Figure 3-11-3 below Figure 3-11-3 Schematic diagram of expansion port J13 Below is the physical picture of the J13 expansion port. Pin1 and Pin2 of the expansion port have been marked on the board.

  • Page 46: 12) Jtag Interface

    The development board has a JTAG interface for downloading FPGA programs or firmware programs to FLASH. In order to protect interface from caused by hot plugging, we added a protection diode to the JTAG signal to ensure that the voltage www.alinx.com 46 / 52 https://innek.ru/...

  • Page 47: 13) Buttons

    AXP100 User Manual of the signal is within the range accepted by the FPGA to avoid damage to the FPGA. Figure 3-12-1 JTAG interface schematic Below is actual picture of the JTAG interface on the expansion board . When plugging or pulling the JTAG cable, be careful not to damage it.

  • Page 48: 14) Leds

    IO voltage connected to the user LED light is configured as a low level, the user LED light is on, and when the connected IO voltage is configured as a high level, the user LED will be off. LED light hardware connection is shown in Figure 3-14-1 www.alinx.com 48 / 52 https://innek.ru/...

  • Page 49: 15) Power Supply

    AXP100 User Manual 3.3V LED1 LED2 LED3 LED4 FPGA Figure 3-14-1 Schematic diagram of LED lamp hardware design Figure 3-14-2 is the physical diagram of 2 user LED lamps on the expansion board Figure 3-14-2 Physical map of user LED light...
  • Page 50 Figure 3-15-1 below: Figure 3-15-1 Schematic diagram of the power supply of the expansion board Figure 3-15-2 is the physical diagram of the power supply circuit on the expansion board Figure 3-15-2 Expansion board power supply circuit www.alinx.com 50 / 52 https://innek.ru/...
  • Page 51 AXP100 User Manual ( 16 ) Fan Because the FPGA chip generates a lot of heat when it is working normally, we added a heat sink and a fan to prevent overheating. The control of the fan is done by the FPGA chip.
  • Page 52 Контакты Контакты для технических и коммерческих вопросов ООО «Инэк» г. Санкт-Петербург, ул. Яблочкова, д. 20, литер А, оф. 504 contact@innek.ru +7 (812) 200-40-37 www.alinx.com 52 / 52 https://innek.ru/...

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