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Alinx ZYNQUltraScale+ AXU5EVB-E User Manual

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ZYNQ UltraScale+ MPSoC
FPGA Development Board
AXU5EVB-E
User Manual

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Summary of Contents for Alinx ZYNQUltraScale+ AXU5EVB-E

  • Page 1 ZYNQ UltraScale+ MPSoC FPGA Development Board AXU5EVB-E User Manual...

  • Page 2: Version Record

    AXU5EVB-E User Manual Version Record Version Date Release By Description Rev 1.0 2021-06-17 Rachel Zhou First Release www.alinx.com 2 / 58...

  • Page 3: Table Of Contents

    Part 3.8: Expansion Header ............... 45 Part 3.9: CAN communication interface ..........47 Part 3.10: 485 communication interface ..........48 Part 3.11: MIPI camera interface ............49 Part 3.12: JTAG Debug Port ...............51 Part 3.13: Real-time clock ..............51 www.alinx.com 3 / 58...
  • Page 4 Part 3.14: EEPROM and Temperature sensor ........52 Part 3.15: User LEDs ................53 Part 3.16: Keys ................... 54 Part 3.17: DIP Switch Configuration ...........55 Part 3.18: Power Supply ..............56 Part 3.19: ALINX Customized Fan ............. 57 Part 3.20: Carrier Board Size Dimension ...........58 www.alinx.com 4 / 58...
  • Page 5 It is a "professional" ZYNQ development platform. For high-speed data transmission and exchange, pre-verification and post-application of data processing is possible. This product is very suitable for students, engineers and other groups engaged in MPSoCs development. www.alinx.com 5 / 58...

  • Page 6: Part 1: Fpga Development Board Introduction

    Ethernet interfaces, 1 SD card slot, 2-Channel 40-pin expansion header, 2-Channel CAN bus interfaces, 2-Channel RS485 bus interfaces, 1 MIPI Camera Interface and some keys and LEDs. The following figure shows the structure of the entire development system: www.alinx.com 6 / 58...
  • Page 7 1 PCIEx1 standard M.2 interface, used to connect M.2 SSD solid state drives, with a communication speed of up to 6Gbps.  DP Output Interface 1 standard Display Port output display interface, used for video image display. Supports up to 4K@30Hz or 1080P@60Hz output www.alinx.com 7 / 58...
  • Page 8  40-pin expansion port 2 40-pin 0.1-inch pitch expansion port can be connected to various ALINX modules (binocular camera, TFT LCD screen, high-speed AD module, etc.). The expansion port contains 1-channel 5V power supply, 2-channel 3.3V power supply, 3-channel way ground, 34 IOs port.
  • Page 9 There are 1 power indicator and 1 DONE Configuration indicator on the core board, 1 power indicator on the carrier board. There are 1 power indicator and 2 user indicators on the carrier board.  KEYs 3 KEYs, include 1 Rest KEY and 2 User KEYs. www.alinx.com 9 / 58...

  • Page 10: Part 2: Acu5Ev Core Board

    PL side (HP I/O: 96, HD I/O: 84). The wiring between the XCZU5EV chip and the interface has been processed with equal length and differential, and the core board size is only 3.15*2.36 (inch), which is very suitable for secondary development. www.alinx.com 10 / 58...

  • Page 11: Part 2.2: Zynq Chip

    PCIE Gen2, USB3.0, SATA 3.1, DisplayPort; it also supports USB2.0 , Gigabit Ethernet, SD/SDIO, I2C, CAN, UART, GPIO and other interfaces. The PL end contains a wealth of programmable logic units, DSP and internal RAM. . Figure 2-2-1 detailed the Overall Block Diagram of the ZU5EV Chip. www.alinx.com 11 / 58...
  • Page 12  Image Video Processor Mali-400 MP2, speed up to 677MHz, 64KB level 2 cache  External storage interface, support 32/64bit DDR4/3/3L, LPDDR4/3 interface  Static storage interface, support NAND, 2xQuad-SPI FLASH.  High-speed connection interface, support PCIe Gen2 x 4, 2 x USB3.0, www.alinx.com 12 / 58...

  • Page 13: Part 2.3: Ddr4 Dram

    MT40A512M16LY-062E, of which 4 DDR4 chips are mounted on the PS side to form a 64-bit data bus bandwidth and 4GB capacity. One DDR4 chip is mounted on the PL end, which is a 16-bit data bus width and a capacity www.alinx.com 13 / 58...
  • Page 14 PCB design to ensure high-speed and stable operation of DDR4. The hardware connection of DDR4 SDRAM on the PS Side is shown in Figure 2-3-1: Figure 2-3-1: PS DDR4 DRAM schematic diagram www.alinx.com 14 / 58...
  • Page 15 PS_DDR4_DQS0_P PS_DDR_DQS_P0_504 AF21 PS_DDR4_DQS0_N PS_DDR_DQS_N0_504 AG21 PS_DDR4_DQS1_P PS_DDR_DQS_P1_504 AF23 PS_DDR4_DQS1_N PS_DDR_DQS_N1_504 AG23 PS_DDR4_DQS2_P PS_DDR_DQS_P2_504 AF25 PS_DDR4_DQS2_N PS_DDR_DQS_N2_504 AF26 PS_DDR4_DQS3_P PS_DDR_DQS_P3_504 AE27 PS_DDR4_DQS3_N PS_DDR_DQS_N3_504 AF27 PS_DDR4_DQS4_P PS_DDR_DQS_P4_504 PS_DDR4_DQS4_N PS_DDR_DQS_N4_504 PS_DDR4_DQS5_P PS_DDR_DQS_P5_504 PS_DDR4_DQS5_N PS_DDR_DQS_N5_504 PS_DDR4_DQS6_P PS_DDR_DQS_P6_504 PS_DDR4_DQS6_N PS_DDR_DQS_N6_504 www.alinx.com 15 / 58...
  • Page 16 PS_DDR4_DQ20 PS_DDR_DQ20_504 AG26 PS_DDR4_DQ21 PS_DDR_DQ21_504 AH25 PS_DDR4_DQ22 PS_DDR_DQ22_504 AH26 PS_DDR4_DQ23 PS_DDR_DQ23_504 AG25 PS_DDR4_DQ24 PS_DDR_DQ24_504 AH27 PS_DDR4_DQ25 PS_DDR_DQ25_504 AH28 PS_DDR4_DQ26 PS_DDR_DQ26_504 AF28 PS_DDR4_DQ27 PS_DDR_DQ27_504 AG28 PS_DDR4_DQ28 PS_DDR_DQ28_504 AC27 PS_DDR4_DQ29 PS_DDR_DQ29_504 AD27 PS_DDR4_DQ30 PS_DDR_DQ30_504 AD28 PS_DDR4_DQ31 PS_DDR_DQ31_504 AC28 www.alinx.com 16 / 58...
  • Page 17 PS_DDR4_DQ49 PS_DDR_DQ49_504 PS_DDR4_DQ50 PS_DDR_DQ50_504 PS_DDR4_DQ51 PS_DDR_DQ51_504 PS_DDR4_DQ52 PS_DDR_DQ52_504 PS_DDR4_DQ53 PS_DDR_DQ53_504 PS_DDR4_DQ54 PS_DDR_DQ54_504 PS_DDR4_DQ55 PS_DDR_DQ55_504 PS_DDR4_DQ56 PS_DDR_DQ56_504 PS_DDR4_DQ57 PS_DDR_DQ57_504 PS_DDR4_DQ58 PS_DDR_DQ58_504 PS_DDR4_DQ59 PS_DDR_DQ59_504 PS_DDR4_DQ60 PS_DDR_DQ60_504 PS_DDR4_DQ61 PS_DDR_DQ61_504 PS_DDR4_DQ62 PS_DDR_DQ62_504 PS_DDR4_DQ63 PS_DDR_DQ63_504 PS_DDR4_DM0 PS_DDR_DM0_504 AG20 PS_DDR4_DM1 PS_DDR_DM1_504 AE23 www.alinx.com 17 / 58...
  • Page 18 PS_DDR_A12_504 AB25 PS_DDR4_A13 PS_DDR_A13_504 AB26 PS_DDR4_WE_B PS_DDR_A14_504 AB24 PS_DDR4_CAS_B PS_DDR_A15_504 AC24 PS_DDR4_RAS_B PS_DDR_A16_504 AC23 PS_DDR4_ACT_B PS_DDR_ACT_N_504 PS_DDR4_ALERT_B PS_DDR_ALERT_N_504 PS_DDR4_BA0 PS_DDR_BA0_504 PS_DDR4_BA1 PS_DDR_BA1_504 PS_DDR4_BG0 PS_DDR_BG0_504 PS_DDR4_CS0_B PS_DDR_CS_N0_504 PS_DDR4_ODT0 PS_DDR_ODT0_504 PS_DDR4_PARITY PS_DDR_PARITY_504 PS_DDR4_RESET_B PS_DDR_RST_N_504 PS_DDR4_CLK0_P PS_DDR_CK0_P_504 PS_DDR4_CLK0_N PS_DDR_CK0_N_504 www.alinx.com 18 / 58...
  • Page 19 PL_DDR4_DQ8 IO_L18N_T2U_N11_AD2N_64 PL_DDR4_DQ9 IO_L18P_T2U_N10_AD2P_64 PL_DDR4_DQ10 IO_L17N_T2U_N9_AD10N_64 PL_DDR4_DQ11 IO_L17P_T2U_N8_AD10P_64 PL_DDR4_DQ12 IO_L15N_T2L_N5_AD11N_64 PL_DDR4_DQ13 IO_L15P_T2L_N4_AD11P_64 PL_DDR4_DQ14 IO_L14N_T2L_N3_GC_64 PL_DDR4_DQ15 IO_L14P_T2L_N2_GC_64 PL_DDR4_DM0 IO_L19P_T3L_N0_DBC_AD9P_64 PL_DDR4_DM1 IO_L13P_T2L_N0_GC_QBC_64 PL_DDR4_A0 IO_L8N_T1L_N3_AD5N_64 PL_DDR4_A1 IO_L3P_T0L_N4_AD15P_64 PL_DDR4_A2 IO_L8P_T1L_N2_AD5P_64 PL_DDR4_A3 IO_L3N_T0L_N5_AD15N_64 PL_DDR4_A4 IO_L11P_T1U_N8_GC_64 PL_DDR4_A5 IO_L4P_T0U_N6_DBC_AD7P_64 PL_DDR4_A6 IO_L9N_T1L_N5_AD12N_64 PL_DDR4_A7 IO_L2P_T0L_N2_64 www.alinx.com 19 / 58...

  • Page 20: Part 2.4: Qspi Flash

    QSPI FLASH are shown in Table 2-4-1. Position Model Capacity Factory MT25QU256ABA1EW9 256Mbit Winbond Table 2-4-1: QSPI FLASH Specification QSPI FLASH is connected to the GPIO port of the BANK500 in the PS www.alinx.com 20 / 58...

  • Page 21: Part 2.5: Emmc Flash

    FLASH, it can be used as a large-capacity storage device in the ZYNQ system, such as storing ARM applications, system files and other user data files The specific models and related parameters of eMMC FLASH are shown in Table 2-5-1. www.alinx.com 21 / 58...
  • Page 22 2-5-1 shows the part of eMMC Flash in the schematic diagram. Figure 2-5-1: QSPI Flash in the schematic Configuration Chip pin assignment: Signal Name Pin Name Pin Number MIO0_QSPI0_SCLK PS_MIO0_500 AG15 MIO1_QSPI0_IO1 PS_MIO1_500 AG16 MIO2_QSPI0_IO2 PS_MIO2_500 AF15 MIO3_QSPI0_IO3 PS_MIO3_500 AH15 MIO4_QSPI0_IO0 PS_MIO4_500 AH16 MIO5_QSPI0_SS_B PS_MIO5_500 AD16 www.alinx.com 22 / 58...

  • Page 23: Part 2.6: Clock Configuration

    PS system. The crystal is connected to the PS_PADI_503 and PS_PADO_503 pins of BANK503 of the ZYNQ chip. The schematic diagram is shown in Figure 2-6-2: Figure 2-6-2: Passive Crystal Oscillator for RTC www.alinx.com 23 / 58...
  • Page 24 (MRCC) of PL BANK64. This global clock can be used to drive the DDR4 controller and user logic circuits in the FPGA. The schematic diagram of this clock source is shown in Figure 2-6-4 www.alinx.com 24 / 58...

  • Page 25: Part 2.7: Led

    FPGA configuration program, the configuration LED light will light up. The LED Schematic in the Core Board is shown in Figure 2-7-1: Figure 2-7-1: LED Schematic in the Core Board www.alinx.com 25 / 58...

  • Page 26: Part 2.8: Power Supply

    TPS6508641 to generate all the power required by the XCZU5EV chip. For the TPS6508641 power supply design, please refer to the power supply chip manual. The design block diagram is as follows: In addition, the VCCIO power supply of BANK65 and BANK66 of www.alinx.com 26 / 58...

  • Page 27: Part 2.9: Acu5Ev Core Board Size Dimension

    IO of BANK25, BANK26, BANK66 and the transceiver signal of BANK505 MGT, J31 is connected to the IO of BANK24 and BANK44, J32 is connected to the MIO, VCCO_65, VCCO_66 and +12V power supply of PS. www.alinx.com 27 / 58...
  • Page 28 B65_L2_N B65_L22_P B65_L2_P B65_L22_N B65_L4_N B65_L20_P B65_L4_P B65_L20_N B65_L1_N B65_L6_N B65_L1_P B65_L6_P B65_L7_P B65_L17_P B65_L7_N B65_L17_N B65_L15_P B65_L9_P B65_L15_N B65_L9_N B65_L16_P B65_L3_N B65_L16_N B65_L3_P B65_L14_P B65_L19_P B65_L14_N B65_L19_N B65_L5_N B65_L18_P B65_L5_P B65_L18_N B65_L11_N B65_L8_P B65_L11_P B65_L8_N www.alinx.com 28 / 58...
  • Page 29 B66_L1_P B65_L13_N B66_L1_N B65_L13_P B66_L6_P B65_L21_P B66_L6_N B65_L21_N B66_L16_P B65_L23_P B66_L16_N B65_L23_N B66_L15_P B66_L5_N B66_L15_N B66_L5_P B66_L4_P B66_L2_P B66_L4_N B66_L2_N B66_L11_P B66_L20_P B66_L11_N B66_L20_N B66_L12_P B66_L7_P B66_L12_N B66_L7_N B66_L13_N B66_L10_P B66_L13_P B66_L10_N B66_L8_N B66_L9_P B66_L8_P B66_L9_N www.alinx.com 29 / 58...
  • Page 30 B66_L19_P B66_L21_P B66_L24_P B66_L17_P B66_L24_N B66_L17_N B66_L23_N B25_L9_P B66_L23_P B25_L9_N B25_L5_N B25_L10_P B25_L5_P B25_L10_N B66_L18_N B25_L12_P B66_L18_P B25_L12_N B25_L4_N B25_L11_P B25_L4_P B25_L11_N B26_L11_P B25_L6_N B26_L11_N B25_L6_P B26_L10_N B26_L6_N B26_L10_P B26_L6_P B26_L7_N B26_L3_N B26_L7_P B26_L3_P B26_L9_N B26_L2_N www.alinx.com 30 / 58...
  • Page 31 505_RX2_N 505_RX0_N Pin assignment of board to board connector J31 J31 Pin Signal Name Pin Number J31 Pin Signal Name Pin Number B24_L10_P B24_L7_P AA13 B24_L10_N B24_L7_N AB13 B24_L6_P AC14 B44_L6_P AC12 B24_L6_N AC13 B44_L6_N AD12 www.alinx.com 31 / 58...
  • Page 32 AH12 B44_L10_P B44_L3_N AH11 B24_L11_N B44_L1_N AH10 B24_L11_P B44_L1_P AG10 B24_L9_N B24_L4_P AE13 B24_L9_P B24_L4_N AF13 B24_L8_P AB15 B44_L5_P AE12 B24_L8_N AB14 B44_L5_N AF12 B44_L2_N AG11 B44_L4_N AF10 B44_L2_P AF11 B44_L4_P AE10 VBAT_IN B44_L11_P B44_L11_N PS_POR_B www.alinx.com 32 / 58...
  • Page 33 Pin assignment of board to board connector J32 J32 Pin Signal Name Pin Number J32 Pin Signal Name Pin Number PS_MIO35 PS_MIO30 PS_MIO29 PS_MIO31 PS_MIO58 PS_MIO53 PS_MODE0 PS_MIO52 PS_MODE1 PS_MIO55 PS_MODE2 PS_MIO56 PS_MODE3 PS_MIO57 PS_MIO36 PS_MIO54 PS_MIO37 PS_MIO27 www.alinx.com 33 / 58...
  • Page 34 PS_MIO38 PS_MIO63 PS_MIO65 PS_MIO40 PS_MIO66 PS_MIO44 PS_MIO67 PS_MIO45 PS_MIO68 PS_MIO47 PS_MIO64 PS_MIO48 PS_MIO69 PS_MIO41 PS_MIO74 PS_MIO32 PS_MIO73 PS_MIO46 PS_MIO72 PS_MIO50 PS_MIO71 PS_MIO49 PS_MIO75 PS_MIO34 PS_MIO70 PS_MIO26 PS_MIO43 PS_MIO24 AB19 PS_MIO51 PS_MIO25 AB21 PS_MIO42 PS_MIO33 VCCO_65 VCCO_66 www.alinx.com 34 / 58...
  • Page 35 AXU5EVB-E User Manual VCCO_65 VCCO_66 VCCO_65 VCCO_66 +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V www.alinx.com 35 / 58...

  • Page 36: Part 3: Carrier Board

     2-Channel 10/100M/1000M Ethernet RJ-45 interface  2-Channel USB Uart Interfaces  1-Channel Micro SD card slot  1-Channel MIPI camera interface  2-Channel 40-pin expansion port  2-Channel CAN communication interfaces  2-Channel 485 communication interfaces www.alinx.com 36 / 58...

  • Page 37: Part 3.2: M.2 Interface

    LANE1 of MGT in a differential signal mode. The PCIE clock is provided by the Si5332 chip, the frequency is 100Mhz, and the schematic diagram of the M.2 circuit design is shown in Figure 3-2-1: Figure 3-2-1: M.2 Interface Schematic www.alinx.com 37 / 58...

  • Page 38: Part 3.3: Dp Interface

    MGT are connected to the DP connector in a differential signal mode. The DisplayPort auxiliary channel is connected to the MIO pin of the PS. The schematic diagram of the DP output interface design is shown in Figure 3-3-1: www.alinx.com 38 / 58...
  • Page 39 DP Reference Clock 505_CLK1_P 505_CLK2_P Positive DP Reference Clock 505_CLK1_N 505_CLK2_N Negative DP_AUX_OUT PS_MIO27 DP Auxiliary Data Output DP_AUX_IN PS_MIO30 DP Auxiliary Data Input DP_OE PS_MIO29 DP Auxiliary Data Output Enable DP_HPD PS_MIO28 DP Insertion Signal Detection www.alinx.com 39 / 58...

  • Page 40: Part 3.4: Usb3.0 Interface

    Signal Name Pin Name Pin Number Description USB_SSTXP 505_TX1_P USB3.0 Data Transmit Positive USB_SSTXN 505_TX1_N USB3.0 Data Transmit Negative USB_SSRXP 505_RX1_P USB3.0 Data Receive Positive USB_SSRXN 505_RX1_N USB3.0 Data Receive Negative USB_DATA0 PS_MIO56 USB2.0 Data Bit0 www.alinx.com 40 / 58...

  • Page 41: Part 3.5: Gigabit Ethernet Interface

    When the JL2121-N040I is powered on, it will detect the level status of some specific IOs to determine its own operating mode. Table 3-5-1 describes the default settings after the GPHY chip is powered on. Configuration Pin Instructions Configuration value RXD3_ADR0 MDIO/MDC Mode PHYaddress PHY Address 001 RXC_ADR1 www.alinx.com 41 / 58...
  • Page 42 25Mhz. Data is sampled on the rising edge and falling samples of the clock. Figure 3-5-1: ZYNQ PS system and GPHY connection diagram The Gigabit Ethernet pin assignments are as follows: Signal Name Pin Name Pin Number Description www.alinx.com 42 / 58...

  • Page 43: Part 3.6: Usb To Serial Port

    The AXU5EVB-E carrier board is equipped with two Uart to USB ports, one is connected to the PS end, and one is connected to the PL end. The conversion chip uses Silicon Labs CP2102GM's USB-UAR chip, and www.alinx.com 43 / 58...

  • Page 44: Part 3.7: Sd Card Slot Interface

    Part 3.7: SD Card Slot Interface The AXU5EVB-E FPGA Development Board contains a Micro SD card interface to provide user access to the SD card memory, the BOOT program for the ZU4EV chip, the Linux operating system kernel, the file www.alinx.com 44 / 58...

  • Page 45: Part 3.8: Expansion Header

    Part 3.8: Expansion Header The AXU5EVB-E board is reserved with two 0.1-inch standard pitch 40-pin expansion ports J45 and J46, which are used to connect the ALINX modules or the external circuit designed by the user. The expansion port has 40 signals, of www.alinx.com...
  • Page 46 B46_L9_P B46_L5_N B46_L5_P B46_L1_N B46_L1_P +3.3V +3.3V J46 Expansion Header Pin Assignment J46 Pin Signal Name Pin Number J46 Pin Signal Name Pin Number B43_L2_N AG11 B43_L2_P AF11 B44_L8_N AB14 B44_L8_P AB15 B44_L9_N B44_L9_P B44_L11_N B44_L11_P www.alinx.com 46 / 58...

  • Page 47: Part 3.9: Can Communication Interface

    MIO interface of the BANK501 on the PS system side. The CAN transceiver chip selected TI's SN65HVD232C chip for user CAN communication services. The connection of the CAN transceiver chip on the PS side is show as Figure 3-9-1 www.alinx.com 47 / 58...

  • Page 48: Part 3.10: 485 Communication Interface

    BANK43~45 on the PL system. The 485 transceiver chip selects the MAX3485 chip from MAXIM for the user's 485 communication service. Figure 3-10-1 is the connection diagram of the 485 transceiver chip on the PL side www.alinx.com 48 / 58...

  • Page 49: Part 3.11: Mipi Camera Interface

    Part 3.11: MIPI camera interface The AXU5EVB-E carrier board includes a MIPI camera interface, which can be used to connect with the ALINX Brand MIPI OV5640 camera module AN5641. MIPI interface 15PIN FPC connector, 2 LANE data and 1 pair of clock, connected to the differential IO pin of BANK65, the level standard is 1.2V;...
  • Page 50 MIPI Input Date LANE1 Positive MIPI_LAN1_N B65_L3_N MIPI Input Date LANE1 Negative CAM_GPIO B43_L4_P AE10 GPIO Control of Camera CAM_CLK B43_L4_N AF10 Clock Input of Camera CAM_SCL B43_L11_P I2C Clock of Camera CAM_SDA B43_L11_N I2C Data of Camera www.alinx.com 50 / 58...

  • Page 51: Part 3.12: Jtag Debug Port

    External need to connect a 32.768KHz passive clock to provide an accurate clock source to the internal clock circuit, so that the RTC can accurately provide clock information. At the same time, in order for the real-time clock to operate www.alinx.com 51 / 58...

  • Page 52: Part 3.14: Eeprom And Temperature Sensor

    Semiconductor. The temperature accuracy of the LM75 chip is 0.5 degrees. The EEPROM and temperature sensor are mounted on the Bank500 MIO of ZYNQ UltraScale+ through the I2C bus. Figure 3-14-1 is the schematic diagram of EEPROM and temperature sensor www.alinx.com 52 / 58...

  • Page 53: Part 3.15: User Leds

    When the IO voltage of the connected user LED light is low, the user LED light is off, and when the connected IO voltage is high, the user LED will be lit. The schematic diagram of the user's LED light hardware connection is shown in Figure 3-15-1: www.alinx.com 53 / 58...

  • Page 54: Part 3.16: Keys

    One user KEY is connected to the MIO of the PS, and one is connected to the IO of the PL. The reset KEY and the user KEYs are both low-level active. The connection diagram of the user key is shown in Figure 3-16-1: www.alinx.com 54 / 58...

  • Page 55: Part 3.17: Dip Switch Configuration

    The user can select different startup modes through the DIP switch SW1 on the expansion board. The SW1 startup mode configuration is shown in the following table 3-17-1. MODE[3:0] Start mode Dial Position （1， 2， 3, 4） 0000 PS JTAG ON，ON，ON，ON www.alinx.com 55 / 58...

  • Page 56: Part 3.18: Power Supply

    BANK65, and the power supply of BANK66 is +1.8V. The schematic diagram of the power supply design on the board is shown in Figure 3-18-1: Figure 3-18-1: Carrier Board Power Schematic The functions of each power distribution are shown in the following table: www.alinx.com 56 / 58...

  • Page 57: Part 3.19: Alinx Customized Fan

    Ethernet, USB2.0, SD, DP, CAN, RS485 +1.2V BANK65 of Core Board Part 3.19: ALINX Customized Fan Because AXU5EVB-E generates a lot of heat when it works normally, we add a heat sink and fan to the chip on the board to prevent the chip from overheating.

  • Page 58: Part 3.20: Carrier Board Size Dimension

    AXU5EVB-E User Manual Part 3.20: Carrier Board Size Dimension Figure 3-20-1: Top View www.alinx.com 58 / 58...

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