Alinx AX7Z035B User Manual page 40

AX7Z035B User Manual
PS side Gigabit Ethernet pin assignment:
Signal Name ZYNQ Pin Name
PHY1_TXCK
PHY1_TXD0
PHY1_TXD1
PHY1_TXD2
PHY1_TXD3
PHY1_TXCTL
PHY1_RXCK
PHY1_RXD0
PHY1_RXD1
PHY1_RXD2
PHY1_RXD3
PHY1_RXCTL
PHY1_MDC
PHY1_MDIO
PHY1_RESET
PL side Gigabit Ethernet pin assignment：
Signal Name
PHY2_TXCK
PHY2_TXD0
PHY2_TXD1
PHY2_TXD2
PHY2_TXD3
PHY2_TXCTL
PHY2_RXCK
PHY2_RXD0
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PS_MIO16_501
PS_MIO17_501
PS_MIO18_501
PS_MIO19_501
PS_MIO20_501
PS_MIO21_501
PS_MIO22_501
PS_MIO23_501
PS_MIO24_501
PS_MIO25_501
PS_MIO26_501
PS_MIO27_501
PS_MIO52_501
PS_MIO53_501
PS_MIO7_500
ZYNQ Pin Name
B35_L23_P
B35_L2_P
B35_L2_N
B35_L6_P
B35_L6_N
B35_L23_N
B35_L11_P
B35_L24_P
ZYNQ Pin Number
G21
G17
G20
G19
H19
F22
G22
F20
J19
F19
H17
F18
A20
A19
E23
ZYNQ Pin Number
C11
E10
D10
F13
E13
B11
G14
A13
Description
RGMII Transmit Clock
Transmit data bit0
Transmit data bit1
Transmit data bit2
Transmit data bit3
Transmit enable signal
RGMII Receive Clock
Receive data Bit0
Receive data Bit1
Receive data Bit2
Receive data Bit3
Receive data valid
signal
MDIO Management
clock
MDIO Management
data
Reset signal
Description
RGMII Transmit Clock
Transmit data bit0
Transmit data bit1
Transmit data bit2
Transmit data bit3
Transmit enable
signal
RGMII Receive Clock
Receive data Bit0
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