Jtag Debugging Port; Dip Switch Configuration - Alinx AX7Z035B User Manual

3.13 JTAG Debugging Port

A JTAG interface is reserved on the carrier board for downloading ZYNQ
programs or solidifying programs to FLASH. To prevent damage to the ZYNQ chip
caused by hot-plugging or unplugging, we have added protective diodes to the
JTAG signal to ensure that the signal voltage is within the range accepted by the
FPGA and avoid damage to the ZYNQ chip.
Users can connect the PC and JTAG interface through the USB downloader
provided by us for ZYNQ system debugging. When plugging and unplugging JTAG
cables, be careful not to hot plug and unplug them.

3.14 DIP Switch Configuration

There is a dip switch SW1 on the development board to configure the boot
mode of the ZYNQ system. The board has three boot modes: JTAG debug mode,
QSPI FLASH and SD card boot mode. When powered on, the XC7Z035 chip detects
the level of the responding MIO ports (MIO5 and MIO4) to determine the boot
mode. Users can select different boot modes through the dip switch SW1 on the
core board. Table 3-14-1 lists the boot mode configuration of SW1.
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Figure 3-13-1: JTAG Interface Schematic
AX7Z035B User Manual
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