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Alinx ARTIX UltraScale+ AXAU15 User Manual

Fpga development board
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ARTIX UltraScale+ FPGA
Development Board
AXAU15
User Manual

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Summary of Contents for Alinx ARTIX UltraScale+ AXAU15

  • Page 1 ARTIX UltraScale+ FPGA Development Board AXAU15 User Manual...
  • Page 2 3.6 TF Card Slot ......................31 3.7 EEPROM 24LC04 ....................32 3.8 JTAG Interface ....................32 3.9 Expansion Port ....................33 3.10 KEYS ........................37 3.11 LED Lights ......................38 3.12 Power Supply ....................39 3.13 Size Dimension ....................40 www.alinx.com 2 / 40...
  • Page 3 It is a "professional" and "versatile" development platform for data communication. We believe that such a product is an ideal for students, engineers and other groups who are engaged in the development of data communication and video image processing. www.alinx.com 3 / 40...
  • Page 4 Also XCAU15P comes with 12 GTH high-speed transceivers, each with a speed of up to 12.5Gb/s, making it very suitable for fiber optic communication and PCIe data communication. The following figure is a schematic diagram of the entire development system structure: www.alinx.com 4 / 40...
  • Page 5 1-Channel Uart to USB interfaces for communication with the computer, for user debugging. The serial port chip adopts the USB-UAR chip of Silicon Labs CP2102GM, and the USB interface adopts the MINI USB 的 USB-UART interface. www.alinx.com 5 / 40...
  • Page 6 This core board uses one Micron's DDR4 Chip MT40A512M16LY-062EIT, with a 16 bit data bus bandwidth and a total capacity of 8Gb; The maximum operating www.alinx.com 6 / 40...
  • Page 7 XCAU15P-2FFVB676I. The speed class is 2 and the temperature class is industrial. This model is a FFVB676 package with 676 pins. The chip naming rules for Xilinx ARTIX UltraScale+ FPGA are shown in Figure 2-2-1 below: www.alinx.com 7 / 40...
  • Page 8 Sitime Corporation, one is at 200MHz and model SiT9121AI-2B1-33E200.00000, used for the system master clock of FPGA and for generating DDR4 control clock; The other one is at 156.25MHz, model SiT9121AI-2B1-33E156.250000, used for the reference clock input of the GTH transceiver. www.alinx.com 8 / 40...
  • Page 9 In Figure 2-3-2, G2 is the 156.25M active differential crystal oscillator circuit, where the clock serves as a reference input clock for the GTH module inside of the FPGA. Crystal oscillator output connected to BANK225 clock pin MGTREFCLK1P of FPGA GTH_ 225 (T7) and MGTREFCLK1N_ 225 (T6). www.alinx.com 9 / 40...
  • Page 10 Table 2-4-1 DDR3 SDRAM Configuration Bit No. Chip Model Capacity Manufacturer MT40A512M16LY-062EIT 512M x 16bit micron The hardware design of DDR4 requires strict consideration of signal integrity. When designing the circuit and PCB, we have fully considered matching www.alinx.com 10 / 40...
  • Page 11 FPGA Pin Name FPGA Pin No. PL_DDR4_A0 IO_L13N_T2L_N1_GC_QBC_66 PL_DDR4_A1 IO_L8N_T1L_N3_AD5N_66 PL_DDR4_A2 IO_L10N_T1U_N7_QBC_AD4N_66 PL_DDR4_A3 IO_L19N_T3L_N1_DBC_AD9N_66 PL_DDR4_A4 IO_L8P_T1L_N2_AD5P_66 PL_DDR4_A5 IO_T3U_N12_66 PL_DDR4_A6 IO_L17P_T2U_N8_AD10P_66 PL_DDR4_A7 IO_L16P_T2U_N6_QBC_AD3P_66 PL_DDR4_A8 IO_L17N_T2U_N9_AD10N_66 PL_DDR4_A9 IO_L12P_T1U_N10_GC_66 PL_DDR4_A10 IO_L15P_T2L_N4_AD11P_66 PL_DDR4_A11 IO_L12N_T1U_N11_GC_66 PL_DDR4_A12 IO_L16N_T2U_N7_QBC_AD3N_66 PL_DDR4_A13 IO_L14N_T2L_N3_GC_66 PL_DDR4_ACT_B IO_L9P_T1L_N4_AD12P_66 www.alinx.com 11 / 40...
  • Page 12 PL_DDR4_DM1 IO_L1P_T0L_N0_DBC_66 PL_DDR4_DQ0 IO_L20P_T3L_N2_AD1P_66 PL_DDR4_DQ1 IO_L21N_T3L_N5_AD8N_66 PL_DDR4_DQ2 IO_L20N_T3L_N3_AD1N_66 PL_DDR4_DQ3 IO_L24N_T3U_N11_66 PL_DDR4_DQ4 IO_L21P_T3L_N4_AD8P_66 PL_DDR4_DQ5 IO_L23P_T3U_N8_66 PL_DDR4_DQ6 IO_L24P_T3U_N10_66 PL_DDR4_DQ7 IO_L23N_T3U_N9_66 PL_DDR4_DQ8 IO_L2P_T0L_N2_66 PL_DDR4_DQ9 IO_L3N_T0L_N5_AD15N_66 PL_DDR4_DQ10 IO_L3P_T0L_N4_AD15P_66 PL_DDR4_DQ11 IO_L2N_T0L_N3_66 PL_DDR4_DQ12 IO_L6P_T0U_N10_AD6P_66 PL_DDR4_DQ13 IO_L5N_T0U_N9_AD14N_66 PL_DDR4_DQ14 IO_L6N_T0U_N11_AD6N_66 PL_DDR4_DQ15 IO_L5P_T0U_N8_AD14P_66 PL_DDR4_DQS0_N IO_L22N_T3U_N7_DBC_AD0N_66 www.alinx.com 12 / 40...
  • Page 13 Figure 2-5-1 is a schematic diagram of the connection between QSPI Flash and FPGA chips. QSPI_CLK FPGA BANK QSPI_CS QSPI FLASH (MT25QU256) QSPI_DQ0~QSPI_DQ3 Figure 2-5-1 QSPI Flash Schematic QSPI Flash pin assignments： Signal Name FPGA Pin Name FPGA Pin No. www.alinx.com 13 / 40...
  • Page 14 IO level to 1.2V (note that these BANK power supplies cannot exceed 1.8V), and the IO levels for BANK84, 85, and 86 are 3.3V. The power supply of the GTH transceiver is generated by the LDO chip. www.alinx.com 14 / 40...
  • Page 15 The sequence of the power is like : VCCINT (1.0V) ->VCCBRAM (1.0V) ->(1.5V, 3.3V, VCCIO) and 1.0V ->MGTAVCC ->MGTAVTT, ensuring the normal operation of the chip. www.alinx.com 15 / 40...
  • Page 16 AF25 1.8V PIN27 B64_L8_P AD23 1.8V PIN28 B64_L3_P AF24 1.8V PIN29 PIN30 PIN31 B64_L7_N AF22 1.8V PIN32 B64_L6_N AC24 1.8V PIN33 B64_L7_P AE22 1.8V PIN34 B64_L6_P AB24 1.8V PIN35 B64_L9_N AC23 1.8V PIN36 B64_L5_N AD25 1.8V www.alinx.com 16 / 40...
  • Page 17 Signal FPGA Level Name Pin No. standard Name Pin No. standard PIN1 B65_L22_N 1.8V PIN2 B65_T2U 1.8V PIN3 B65_L22_P 1.8V PIN4 B65_T1U AA23 1.8V PIN5 B65_L18_N 1.8V PIN6 B65_T0U 1.8V PIN7 B65_L18_P 1.8V PIN8 B65_T3U 1.8V www.alinx.com 17 / 40...
  • Page 18 PIN70 PIN71 FPGA_TCK AE12 1.8V PIN72 B84_L3_N AE15 3.3V PIN73 FPGA_TDI AB12 1.8V PIN74 B84_L3_P AD15 3.3V PIN75 FPGA_TMS AB10 1.8V PIN76 B84_L4_N AD14 3.3V PIN77 FPGA_TDO 1.8V PIN78 B84_L4_P AD13 3.3V PIN79 Null PIN80 Null www.alinx.com 18 / 40...
  • Page 19 3.3V PIN42 B85_L10_N 3.3V PIN43 B85_L8_P 3.3V PIN44 B85_L10_P 3.3V PIN45 B85_L7_N 3.3V PIN46 B85_L12_N 3.3V PIN47 B85_L7_P 3.3V PIN48 B85_L12_P 3.3V PIN49 PIN50 PIN51 B86_L2_N 3.3V PIN52 B86_L1_N 3.3V PIN53 B86_L2_P 3.3V PIN54 B86_L1_P 3.3V www.alinx.com 19 / 40...
  • Page 20 224_RX2_N 1.2V PIN15 224_TX2_P 1.2V PIN16 224_RX2_P 1.2V PIN17 PIN18 PIN19 224_TX3_N 1.2V PIN20 224_RX3_N 1.2V PIN21 224_TX3_P 1.2V PIN22 224_RX3_P 1.2V PIN23 PIN24 PIN25 225_CLK0_N 1.2V PIN26 224_CLK0_N 1.2V PIN27 225_CLK0_P 1.2V PIN28 224_CLK0_P 1.2V www.alinx.com 20 / 40...
  • Page 21 PIN65 PIN66 PIN67 226_TX2_N 1.2V PIN68 226_RX2_N 1.2V PIN69 226_TX2_P 1.2V PIN70 226_RX2_P 1.2V PIN71 PIN72 PIN73 226_TX3_N 1.2V PIN74 226_RX3_N 1.2V PIN75 226_TX3_P 1.2V PIN76 226_RX3_P 1.2V PIN77 PIN78 PIN79 226_CLK0_P 1.2V PIN80 226_CLK0_N 1.2V www.alinx.com 21 / 40...
  • Page 22 AXAU15 User Manual 2.9 Size Dimension TOP View www.alinx.com 22 / 40...
  • Page 23 When the JL2121 is powered on, it will detect the level status of some specific IOs to determine its own operating mode. Figure 3-5-1 describes the default settings after the GPHY chip is powered on. Configuration Pin Instructions Configuration value MDIO/MDC mode PHY Address RXD3_ADR0 PHY Address 001 RXC_ADR1 RXCTL_ADR2 www.alinx.com 23 / 40...
  • Page 24 PHY Chip Reset PHY_RESET B64_T0U AF23 PHY_MDC B64_T1U AF20 MDIO Management Clock PHY_MDIO B64_T2U AE18 MDIO Management Data PHY_RXC B64_L11_P AD21 RGMII Receive Clock Receive Enable Signal PHY_RXDV B64_L11_N AE21 PHY_RXD0 B64_L9_P AC22 Receive Data Bit0 www.alinx.com 24 / 40...
  • Page 25 PC, with a reference clock frequency of 100Mhz. The design diagram of the PCIe interface of the development board is shown in Figure 3-3-1, where the TX sending signal and the reference clock CLK signal are connected in AC coupling mode. www.alinx.com 25 / 40...
  • Page 26 PCIE channel 1 Data Transmit Negative PCIE_TX2_P PCIE channel 2 Data Transmit Positive PCIE_TX2_N PCIE channel 2 Data Transmit Negative PCIE_TX3_P PCIE channel 3 Data Transmit Positive PCIE_TX3_N PCIE channel 3 Data Transmit Negative PCIE_CLK_P PCIE Reference Clock Positive www.alinx.com 26 / 40...
  • Page 27 PCIE Reset Signal 3.4 FMC Expansion Port The AXAU15 FPGA development board comes with a standard FMC HPC expansion port, and can be externally connected to XILINX or ALINX various FMC modules (HDMI input/output modules, binocular camera modules, high-speed AD modules, etc.).
  • Page 28 LA Reference 21 Data P FMC_LA22_N B64_L22_N AC17 LA Reference 22 Data N FMC_LA22_P B64_L22_P AB17 LA Reference 22 Data P FMC_LA23_N B64_L21_N AB20 LA Reference 23 Data N FMC_LA23_P B64_L21_P AA20 LA Reference 23 Data P www.alinx.com 28 / 40...
  • Page 29 FMC Transceiver data reception 1 N FMC_DP1_M2C_P 225_RX1_P FMC Transceiver data reception 1 P FMC_DP2_C2M_N 225_TX2_N FMC Transceiver data transmission 2 N FMC_DP2_C2M_P 225_TX2_P FMC Transceiver data transmission 2 P FMC_DP2_M2C_N 225_RX2_N FMC Transceiver data reception 2 N www.alinx.com 29 / 40...
  • Page 30 MINI USB interface. It can be connected to the USB port of a PC using a USB cable for serial data communication. The schematic diagram of USB Uart circuit design is shown in Figure 3-5-1: www.alinx.com 30 / 40...
  • Page 31 Figure 3-6-1 TF Card Slot Schematic SD Card Slot pin assignment: Signal Name FPGA Pin Name FPGA Pin Name Description SD_CD B65_L8_P SD Clock Signal SD_CLK B65_L9_N AA25 SD Command Signal SD_CMD B65_L9_P AA24 SD Data 0 www.alinx.com 31 / 40...
  • Page 32 The development board reserves a JTAG interface for downloading FPGA programs or solidifying programs to FLASH. In order to prevent damage to the FPGA chip caused by live plugging, we have added protective diodes to the www.alinx.com 32 / 40...
  • Page 33 3.9 Expansion Port The expansion board reserves two 40 pin expansion ports J33 and J34 with a standard spacing of 2.54mm, are used to connect various modules of ALINX or external circuits designed by the user. The expansion port has 40 signals, including 1 5V power supply, 2 3.3V power supplies, 3 ground ports, and 34 IO...
  • Page 34 IO 3.3V J33_14 B85_L4_N IO 3.3V J33_15 B85_L2_P IO 3.3V J33_16 B85_L2_N IO 3.3V J33_17 B85_L1_P IO 3.3V J33_18 B85_L1_N IO 3.3V J33_19 B84_L2_N AF13 IO 3.3V J33_20 B84_L2_P AE13 IO 3.3V J33_21 B84_L1_N AF15 IO 3.3V www.alinx.com 34 / 40...
  • Page 35 J33_36 B84_L8_N AB14 IO 3.3V J33_37 Ground J33_38 Ground J33_39 power source 3.3V J33_40 power source 3.3V The circuit of the expansion port (J34) is shown in Figure 3-9-2 below: Figure 3-9-2 Expansion Port J34 Schematic www.alinx.com 35 / 40...
  • Page 36 J34_25 B86_L3_N IO 3.3V J34_26 B86_L3_P IO 3.3V J34_27 B86_L7_N IO 3.3V J34_28 B86_L7_P IO 3.3V J34_29 B86_L10_N IO 3.3V J34_30 B86_L10_P IO 3.3V J34_31 B86_L6_N IO 3.3V J34_32 B86_L6_P IO 3.3V J34_33 B86_L8_P IO 3.3V www.alinx.com 36 / 40...
  • Page 37 KEY1 FPGA BANK KEY2 KEY2 Figure 3-10-1 Schematic of Key hardware design KEY FPGA pin assignment： Signal Name FPGA Pin Name FPGA Pin No. Description KEY1 B65_T2U User Key 1 KEY2 B65_T1U AA23 User Key 2 www.alinx.com 37 / 40...
  • Page 38 FPGA_DONE BANK0 电平转换 Figure 3-11-1 LED lights hardware connection diagram LED FPGA pin assignment： Signal Name FPGA Pin Name FPGA Pin No. Description LED1 B65_T0U User defined indicator light LED2 B64_T3U AC16 User defined indicator light www.alinx.com 38 / 40...
  • Page 39 ETA1471 1.8V/6A ETA1471 U175 VADJ/3A ETA1471 Figure 3-12-1 Power Supply Design Diagram The VADJ power supply can use a jump cap to change the power voltage to 1.2V and provide separate power to the FMC module. www.alinx.com 39 / 40...
  • Page 40 AXAU15 User Manual 3.13 Size Dimension Top View www.alinx.com 40 / 40...