Alinx AX7Z035B User Manual page 26

AX7Z035B User Manual
BANK12 and BANK13 is generated through two SPX3819M5-3-3 channels. Users can
replace the LDO chip to make the IO input and output of these two BANKs meet
other voltage standards.
The functions of each power distribution are shown in the following table:
Power Supply
+1.0V
+1.8V
+3.3V
+1.5V
VCCIO12
VCCIO13
VREF, VTT
（+0.75V）
MGTAVCC(+1.0V)
MGTAVTT(+1.2V)
MGTVCCAUX
（+1.8V）
Because the power supply of the ZYNQ FPGA has the power-on sequence
requirements, in the circuit design, we have designed according to the power
requirements of the chip. The power-on sequence is +1.0V->+1.8V-> (+1.5 V, +3.3V,
VCCIO12, VCCIO13) circuit design to ensure the normal operation of the chip.
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Function
Core voltage of ZYNQ PS and PL
ZYNQ PS and PL auxiliary voltage,
BANK501，BANK35，eMMC
ZYNQ Bank0,Bank500，QSIP FLASH,
Clock crystal oscillator
DDR3, ZYNQ Bank502, Bank33,
Bank34
ZYNQ Bank12
ZYNQ Bank13
PS DDR3，PL DDR3
ZYNQ Bank111, Bank112
ZYNQ Bank111, Bank112
ZYNQ Bank111, Bank112
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