Check The Setup/Hold With Single Clock, Multiple Clock Edges - HP 1660C Series Service Manual

Testing Performance
To test the single-clock, multiple-edge, state acquisition (logic analyzer)

Check the setup/hold with single clock, multiple clock edges

Select the logic analyzer setup/hold time.
1
a In the logic analyzer Format menu, select Master Clock.
b Select and activate any multiple clock edge.
c Select the Setup/Hold field, then select the setup/hold to be tested for all pods. The
first time through this test, use the top combination in the following table.
Setup/Hold Combinations
4.0/0.0 ns
0.0/4.0 ns
2.0/2.0 ns
d Select Done to exit the setup/hold combinations.
Using the Delay mode of the pulse generator channel 2, position the pulses
2
according to the setup time of the setup/hold combination selected, +0.0 ps or
−100 ps.
a On the Oscilloscope, select [Define meas] Define ∆ Time - Stop edge: rising.
b In the oscilloscope timebase menu, select Position. Using the oscilloscope knob,
position the falling edge of the data waveform so that it is centered on the display.
c On the oscilloscope, select [Shift] ∆ Time. Select Start src: channel 1, then select
[Enter] to display the setup time (∆ Time(1)-(2)).
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