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Testing Performance
To test the multiple-clock, multiple-edge, state acquisition (logic analyzer)
Connect the logic analyzer
Using the 6-by-2 test connectors, connect the first combination of logic analyzer
1
clock and data channels listed in one of the following tables to the pulse generator.
If you are testing an HP 1660C or HP 1661C, you will repeat this test for the second
combination.
Using SMA cables, connect channel 1, channel 2, and trigger of the oscilloscope to
2
the pulse generator.
Connect the HP 1660C/CS/CP or HP 1661C/CS/CP Logic Analyzer to the Pulse Generator
Testing Combinations
1
2
3–40
Connect to
Connect to
HP 8133A
HP 8133A Channel 2
Channel 2 Output
Output
Pod 1, channel 3
Pod 2, channel 3
Pod 3, channel 3
Pod 4, channel 3
Pod 5, channel 3
Pod 6, channel 3
Pod 7, channel 3
Pod 8, channel 3
Pod 1, channel 11
Pod 2, channel 11
Pod 3, channel 11
Pod 4, channel 11
Pod 5, channel 11
Pod 6, channel 11
Pod 7, channel 11
Pod 8, channel 11
Connect to
HP 8133A Channel 1
Output
J-clock
M-clock
N-clock
J-clock
M-clock
N-clock
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