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Testing Performance
To test the single-clock, single-edge, state acquisition (logic analyzer)
Check the data pulse width. Using the oscilloscope, verify that the data pulse width
3
is 3.500 ns, +0 ps or −100 ps.
a On the Oscilloscope, select [Define meas] Define ∆ Time - Stop edge: rising.
b In the oscilloscope timebase menu, select Position. Using the oscilloscope knob,
position the rising edge of the clock waveform so that it is centered on the display.
c On the oscilloscope, select [Shift] ∆ Time, then select [Enter] to display the setup time
(∆ Time(1)-(2)).
d Adjust the pulse generator channel 1 Delay until the pulses are aligned according the
the setup time of the setup/hold combination selected, +0.0 ps or -100 ps.
3–30
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