Check The Setup/Hold With Single Clock, Multiple Clock Edges - HP 1660 Series Service Manual

To test the single-clock, multiple-edge, state acquisition (logic analyzer)

Check the setup/hold with single clock, multiple clock edges

Select the logic analyzer setup/hold time.
1 1
a a In the logic analyzer Format menu, select Master Clock.
b b Select and activate any multiple clock edge.
c c Select the Setup/Hold field, then select the setup/hold to be tested for all pods. The
first time through this test, use the top combination in the following table.
Setup/Hold Combinations
4.0/0.0 ns
0.0/4.0 ns
2.0/2.0 ns
d d Select Done to exit the setup/hold combinations.
Disable the pulse generator channel 1 COMP (with the LED off).
2 2
Using the Delay mode of the pulse generator channel 2, position the pulses according
3 3
to the setup time of the setup/hold combination selected, +0.0 ps or − 100 ps.
a a In the oscilloscope Delta V menu, set the Marker 1 Position to Chan 1, then set
Marker 1 at − 1.3000 V. Set the Marker 2 Position to Chan 2, then set Marker 2 at
− 1.3000 V.
b b In the oscilloscope Delta T menu, select Start on Pos Edge 1. Select Stop on Neg
Edge 1.
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