To Test The Single-Clock, Multiple-Edge, State Acquisition (Logic Analyzer); Set Up The Equipment - HP 1660C Series Service Manual

To test the single-clock, multiple-edge, state acquisition
(logic analyzer)
Testing the single-clock, multiple-edge, state acquisition verifies the performance of
the following specifications:
•
Minimum master to master clock time
•
Maximum state acquisition speed
•
Setup/Hold time for single-clock, multiple-edge, state acquisition
•
Minimum clock pulse width
This test checks two combinations of data using a multiple-edge single clock at three
selected setup/hold times.
Equipment Required
Equipment
Pulse Generator
Digitizing Oscilloscope
Adapter
SMA Coax Cable (Qty 3)
Coupler
BNC Test Connector,
6x2 (Qty 4)

Set up the equipment

Turn on the equipment required and the logic analyzer. Let them warm up for
1
30 minutes before beginning the test if you have not already done so.
Set up the pulse generator according to the following table.
2
Pulse Generator Setup
Timebase Channel 2
Mode: Int Mode: Square
Divide: SQUARE ÷ 2
Period: 10.000 ns
Delay: 0.000 ns
High: −0.90 V
Low: −1.70 V
COMP: Disabled
(LED Off)
Critical Specifications
100 MHz 3.5 ns pulse width, < 600 ps rise time
≥ 6 GHz bandwidth, < 58 ps rise time
SMA(m)-BNC(f)
18 GHz bandwidth
BNC(m)(m)
Period
Divide: Divide ÷ 2
Ampl: 0.50 V
Offs: 0.00 V
Recommended
Model/Part
HP 8133A option 003
HP 54750A, with HP 54751A
plugin
HP 1250-1200
HP 8120-4948
HP 1250-0216
Channel 1
Mode: Pulse
Delay: 0.000 ns
Width: 4.00 ns
High: −0.90 V
Low: −1.70 V
COMP: Disabled
(LED Off)
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