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The HP 1660CP-Series are 100-MHz State/500-MHz Timing Logic Analyzers. Logic Analyzer Features • 130 data channels and 6 clock/data channels in the HP 1660CP • 96 data channels and 6 clock/data channels in the HP 1661CP • 64 data channels and 4 clock/data channels in the HP 1662CP •...
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Logic Analyzer Overview Connecting Peripherals Using the Logic Analyzer This User’s Guide shows you how to use the HP 1660CP-Series Logic Analyzer. It contains measurement examples, field Using the Trigger Menu and feature definitions, and a basic service guide. Refer to this manual for...
2 Connecting Peripherals To connect a mouse 2–3 To connect a keyboard 2–4 To connect to an HP-IB printer 2–5 To connect to an RS-232-C printer 2–7 To connect to a parallel printer 2–8 To connect to a controller 2–9 3 Using the Logic Analyzer Accessing the Menus 3–3...
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Contents 4 Using the Trigger Menu Specifying a Basic Trigger 4–3 To assign terms to an analyzer 4–4 To define a term 4–5 To change the trigger specification 4–6 Changing the Trigger Sequence 4–7 To add sequence levels 4–8 To change macros 4–9 Setting Up Time Correlation between Analyzers 4–10 To set up time correlation between two state analyzers 4–11 To set up time correlation between a timing and a state analyzer 4–11...
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Contents 5 Using the Pattern Generator Setting Up the Proper Configurations 5–3 To set up the configuration 5–3 To build a label 5–5 Building Test Vectors and Macros 5–6 To build a main vector sequence 5–7 To build an initialization sequence 5–8 To edit a main or initialization sequence 5–8 To include hardware instructions in a sequence 5–9 To include software instructions in a sequence 5–10...
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Contents Loading ASCII Files 5–36 ASCII File Commands 5–37 ASCDown Command 5–37 LABel 5–38 VECTor 5–39 FORMat:xxx 5–41 Loading an ASCII file over a bus (example) 5–42 Pattern Generator Probing System 5–44 Pod Numbering 5–44 Connecting Pods Directly to a PC Board 5–45 Output Pod Characteristics 5–46 6 Triggering Examples Single-Machine Trigger Examples 6–3...
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Contents Cross-Arming Trigger Examples 6–22 To examine software execution when a timing violation occurs 6–23 To look at control and status signals during execution of a routine 6–24 To detect a glitch 6–25 To trigger timing analysis of a count-down on a set of data lines 6–26 To monitor two coprocessors in a target system 6–27 Special Displays 6–28 To interleave trace lists 6–29...
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Disk operations 8–21 Autoload 8–23 Format 8–23 Pack 8–23 Load and Store 8–24 The RS-232-C, HP-IB, and Centronics Interfaces 8–25 The HP-IB interface 8–26 The RS-232-C interface 8–26 The Centronics interface 8–27 System Utilities 8–28 Real Time Clock Adjustments field 8–28 Update FLASH ROM field 8–28...
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Contents The Analyzer Format Menu 8–32 Pod threshold field 8–32 State acquisition modes (state only) 8–33 Timing acquisition modes (timing only) 8–34 Clock Inputs Display 8–35 Pod clock field (State only) 8–35 Master and Slave Clock fields (State only) 8–38 Symbols field 8–41 Label fields 8–42 Label polarity fields 8–43...
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Contents The Mixed Display Menu 8–63 Interleaving state listings 8–63 Time-correlated displays 8–64 Markers 8–64 The Chart Menu 8–65 Min and Max scaling fields 8–66 Markers/Range field 8–66 The Compare Menu 8–67 Reference Listing field 8–68 Difference Listing field 8–68 Copy Listing to Reference field 8–69 Find Error field 8–69 Compare Full/Compare Partial field 8–69...
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The Trigger Sequence 10–12 Trigger sequence specification 10–13 Analyzer resources 10–15 Timing analyzer 10–18 State analyzer 10–18 Configuration Translation Between HP Logic Analyzers 10–19 The Analyzer Hardware 10–21 HP 1660CP-series analyzer theory 10–22 Logic acquisition board theory 10–25 Pattern Generator board theory 10–28 Self-tests description 10–30...
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Contents 11 Troubleshooting Analyzer Problems 11–3 Intermittent data errors 11–3 Unwanted triggers 11–3 No activity on activity indicators 11–4 Capacitive loading 11–4 No trace list display 11–4 Preprocessor Problems 11–5 Target system will not boot up 11–5 Slow clock 11–6 Erratic trace measurements 11–7 Inverse Assembler Problems 11–8 No inverse assembly or incorrect inverse assembly 11–8...
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Contents 12 Specifications Accessories 12–2 Specifications (logic analyzer) 12–3 Characteristics (logic analyzer) 12–4 Characteristics (pattern generator) 12–4 Supplemental characteristics (logic analyzer) 12–5 13 Operator’s Service Preparing For Use 13–3 To inspect the logic analyzer 13–4 To apply power 13–4 To set the line voltage 13–5 To degauss the display 13–6 To clean the logic analyzer 13–6 To test the logic analyzer 13–6...
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HP 1660CP-Series Logic Analyzer HP 1660CP-Series Logic Analyzer Front Panel Select Key The Select key action depends on the type of field currently highlighted. If the field is an option field, the Select key brings up an option menu or, if there are only two possible values, toggles the value in the field.
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If you are using a mouse, you can do the same actions by holding down the right button of the mouse while dragging. HP 1660CP-Series Logic Analyzer Back Panel Line Power Module Permits selection of 110-120 or 220-240 Vac and contains the fuses for each of these voltage ranges.
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RS-232-C Connector Standard DB-25 type connector for connecting an RS-232-C printer or controller. HP-IB Connector Standard HP-IB connector for connecting an HP-IB printer or controller. Parallel Printer Connector Standard Centronics connector for connecting a parallel printer. LAN Connectors Connects the logic analyzer to your local ethernet network. The BNC connector on top accepts 10Base2 ("thinlan").
Logic Analyzer Overview To make a measurement To make a measurement For more detail on any of the information below, see the referenced chapters or the Logic Analyzer Training Kit. If you are using a preprocessor with the logic analyzer, some of these steps may not apply. Map to target Connect probes Connect probes from the target system to the logic analyzer to physically map the target system to the channels in the logic...
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Logic Analyzer Overview To make a measurement Set up analyzers* Set modes and clocks Set the state and timing analyzers using the Analyzer Format menu. In general, these modes trade channel count for speed or storage. The state analyzer also provides for complicated clocking.
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Logic Analyzer Overview To make a measurement Set up trigger Define terms In the Analyzer Trigger menu, define trigger variables called terms to match specific conditions in your target system. Terms can match patterns, ranges, or edges across multiple labels. Configure Arming Control Use Arming Control if •...
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Logic Analyzer Overview To make a measurement Run measurement Select single or repetitive From any Analyzer menu, select the field labeled Run in the upper right corner to start measuring, or press the Run key. A single run will run once, until memory is full; a repetitive run will go until you select Stop or until a stop measurement condition that you set in the markers menu is fulfilled.
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Logic Analyzer Overview To make a measurement View data Search for patterns In both the Waveform and Listing menus you can use symbols and markers to search for patterns in your data. In the Analyzer Waveform or Analyzer Listing menu, toggle the Markers field to turn the pattern markers on and then specify the pattern.
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Connecting Peripherals Your HP 1660CP-series logic analyzer comes with a PS2 mouse. It also provides connectors for a keyboard, Centronics (parallel) printer, and HP-IB and RS-232-C devices. This chapter tells you how to connect peripheral equipment such as the mouse or a printer to the logic analyzer.
Connecting Peripherals To connect a mouse To connect a mouse Hewlett-Packard supplies a mouse with the logic analyzer. If you prefer a different style of mouse you can use any PS2 mouse with a standard PS2 DIN interface. Plug the mouse into the mouse connector on the back panel. Make sure the plug shows the arrow on top.
Connecting Peripherals To connect a keyboard To connect a keyboard You can use either the HP-recommended keyboard, HP E2427B, or any other keyboard with a standard DIN connector. Plug the keyboard into the keyboard connector on the back panel. To verify, check the System External I/O menu for a keyboard box.
To connect to an HP-IB printer To connect to an HP-IB printer Printers connected to the logic analyzer over HP-IB must support HP-IB and Listen Always. When controlling a printer, the analyzer’s HP-IB port does not respond to service requests (SRQ), so the SRQ enable setting does not have any effect on printer operation.
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Go to the System External I/O menu and configure the analyzer’s printer settings. If the analyzer is not already set to HP-IB, select the field under Connected To: in the Printer box and choose HP-IB from the menu. Select the Printer Settings field.
Push all the switches down to the 0 position. • For the HP ThinkJet printer, the mode switches are on the rear panel of the printer. Push all the switches down to the 0 position. •...
Connecting Peripherals To connect to a parallel printer To connect to a parallel printer Turn off the analyzer and the printer, and connect a parallel printer cable from the printer to the parallel printer connector on the analyzer rear panel. Before turning on the printer, configure the printer for parallel operation.
To connect to a controller To connect to a controller You can control the HP 1660CP-series logic analyzer with another instrument, such as a computer running a program with embedded analyzer commands. The steps below outline the general procedure for connecting to a controller using HP-IB or RS-232-C.
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Using the Logic Analyzer This chapter shows you how to perform the basic tasks necessary to make a measurement. Each section uses an example to show how the task fits into the overall goal of making a measurement. 3–2...
Accessing the Menus When you power up the logic analyzer, the first screen after the system tests is the Analyzer Configuration menu. Menus are identified by two fields in the upper left corner. The leftmost field shows Analyzer. This field is sometimes referred to as the "mode field" because it controls which other set of menus you can access.
Using the Logic Analyzer To access the System menus To access the System menus The System menus allow you to perform operations that affect the entire logic analyzer, such as load configurations, change shades, and perform system diagnostics. Select the mode field. Use the arrow keys to highlight the mode field, then press the Select key.
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• Flexible Disk allows you to perform file operations on the flexible disk. • External I/O allows you to configure your HP-IB, RS-232-C, and LAN interfaces and connect to a printer and controller. • Utilities allows you to set the clock, update the operating system software, and adjust the display.
Using the Logic Analyzer To access the Analyzer menus To access the Analyzer menus The Analyzer menus allow you to control the analyzer to make your measurement, perform operations on the data, and view the results on the display. Select the mode field. A pop-up menu appears with the choices System, Analyzer, and Patt Gen.
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Using the Logic Analyzer To access the Analyzer menus • Mixed Display always appears in the menu list when an analyzer is set to State or Timing, but it requires a State analyzer with time tags enabled. • Waveform is available when an analyzer is set to State or Timing. Use Waveform to view the data as logic levels on discrete lines.
Using the Logic Analyzer To access the Pattern Generator menus To access the Pattern Generator menus The Pattern Generator menus let you configure the pattern generator, build test vector files, and use and create user macros. Select the mode field. A pop-up menu appears with the choices System, Analyzer, and Patt Gen.
The default label names are Lab1 through Lab126. However, you can modify a name to any six-character string. If you are using an HP preprocessor interface, the configuration file has predefined labels for your specific processor.
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Using the Logic Analyzer To label channel groups Select the pod containing the channels for the label. Use the knob or the arrow keys to position the selector over a channel you want to change. An asterisk indicates the channel is selected; a dot indicates the channel is not part of the current group.
Using the Logic Analyzer To create a symbol To create a symbol Symbols are alphanumeric mnemonics that represent specific data patterns or ranges. When you define a symbol and set the the base type to Symbol in the Listing menu, the symbol is displayed in the data listing where the bit pattern would normally be displayed.
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To close the symbol table menu, select Done. Symbol table Menu Showing Three Symbols You can also download symbol tables created by your programming environment using HP E2450A Symbol Utility. The Symbol Utility is shipped with the HP 1660CP-series logic analyzers. See Also HP E2450A Symbol Utility User’s Guide for more information on the...
Using the Logic Analyzer To examine an analyzer waveform To examine an analyzer waveform The Analyzer Waveform menu lets you view state or timing data in a format similar to an oscilloscope display. The horizontal axis represents states (in state mode) or time (in timing mode) and the vertical axis represents logic highs and lows.
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Using the Logic Analyzer To examine an analyzer waveform To take measurements, select the Markers field and choose the appropriate marker type. The markers available depend on the type of analyzer and whether or not tagging is enabled. Use markers to locate patterns quickly. roll indicator trigger indicator memory displayed...
Using the Logic Analyzer To examine an analyzer listing To examine an analyzer listing The Analyzer Listing menu displays state or timing data as patterns (states). The Listing menu uses any of several formats to display the data such as binary, ASCII, or symbols.
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Using the Logic Analyzer To examine an analyzer listing To insert a label, select one of the label fields, then select Insert from the pop-up and the label you want to insert. The last label cannot be deleted, so there is always at least one label. You can insert the same label multiple times and display it in different bases.
Using the Logic Analyzer To compare two listings To compare two listings The Compare menu allows you to take two state analyzer acquisitions and compare them to find the differences. You can use this function to quickly find all the effects after changing the target system or to quickly compare the results of quality tests with results from a working system.
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Using the Logic Analyzer To compare two listings The Difference listing displays the states that are identical in dark typeface, and the states that are different in light typeface (indistinguishable in the above illustration). The light typeface shows the data from the compare file that is different from the data in the reference file.
The Inverse Assembler When the analyzer captures a trace, it captures binary information. The analyzer can then present this information in symbol, binary, octal, decimal, hexadecimal, or ASCII. Or, if given information about the meaning of the data captured, the analyzer can inverse assemble the trace.
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Using the Logic Analyzer To use an inverse assembler The inverse assembler synchronizes at the first line in the trace list... not at the cursor position Inverse Assembly Synchronization When you press the Invasm key to begin inverse assembly of a trace, the inverse assembler begins with the first displayed state in the trace list.
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Using the Logic Analyzer To use an inverse assembler If you roll the trace list to a new position and press Invasm again, the inverse assembler repeats the above process. However, it does not work backward in the trace list from the starting position. This may cause differences in the trace list above and below the point where you synchronized inverse assembly.
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Using the Trigger Menu To use the logic analyzer efficiently, you need to be able to set up your own triggers. This chapter provides examples of triggering. Those examples assume you already know where to find fields in the trigger menu.
Specifying a Basic Trigger The default analyzer triggers are While storing "anystate" TRIGGER on "a" 1 time Store "anystate" for state analyzers and TRIGGER on "a" > 8 ns for timing analyzers. If you want to simply record data, these will get you started.
Using the Trigger Menu To assign terms to an analyzer To assign terms to an analyzer When you turn the logic analyzer on, Analyzer 1 is named Machine 1 and Analyzer 2 is off. Because trigger terms can only be used by one analyzer at a time, all the terms are assigned to Analyzer 1.
Using the Trigger Menu To define a term To define a term Both default triggers trigger on term "a". If you only need to look for the occurrence of a certain state, such as a write to protected memory, then you only need to define term "a"...
Using the Trigger Menu To change the trigger specification To change the trigger specification Most triggers use terms other than "a." Even a simple trigger might use additional terms to set conditions on the actual trigger. To use these terms, you must include them in the trigger sequence specification.
Changing the Trigger Sequence Most measurements require more complicated triggers to better filter information. From the basic trigger, you can: • Add sequence levels • Change macros Your logic analyzer provides a macro library to make setting up the trigger easier. There are 12 state macros and 13 timing macros. Most macros take more than one level internally to implement, and can be broken down into their separate levels.
Using the Trigger Menu To add sequence levels To add sequence levels You can add sequence levels anywhere except after the final one. In the Trigger menu, select the number beside the sequence level just after where you want to insert. For example, if you want to insert a sequence level between levels 1 and 2, you would select level 2.
Using the Trigger Menu To change macros To change macros You do not need to add and delete levels just to change a level’s macro. This can be done from within the Sequence Level pop-up. From the Trigger menu, select the sequence level number of the sequence level you want to modify.
Setting Up Time Correlation between Analyzers There are two possible combinations of analyzers: state and state, and state and timing. Timing and timing is not possible because the Analyzer Configuration menu only permits one analyzer at a time to be configured as a timing analyzer. For either combination, time correlation is necessary for interleaving and mixed display.
Using the Trigger Menu To set up time correlation between two state analyzers To set up time correlation between two state analyzers To correlate the data between two state analyzers, both must have Count Time turned on in their Trigger menus. Although both have Count State available, it is not possible to correlate data based on states even when they are identically defined.
Arming and Additional Instruments Occasionally you may need to start the analyzer acquiring data when another instrument detects a problem. Or, you may want to have the analyzer itself arm another measuring tool. This is accomplished from the Arming Control field of the Analyzer Trigger menu. To arm another instrument Attach a BNC cable from the External Trigger Output port on the back of the logic analyzer to the instrument you want to trigger.
Using the Trigger Menu To receive an arm signal from another instrument To receive an arm signal from another instrument When you set the analyzer to wait for an arm signal, it does not react to data that would normally trigger it until after it has received the arm signal. The arm signal can be sent to any of the Trigger Sequence levels, but will go to level 1 unless you change it.
Managing Memory Sometimes you will need every last bit of memory you can get on the logic analyzer. There are three simple ways to maximize memory when specifying your trigger: • Selectively store branch conditions (State only) • Place the trigger relative to memory •...
Using the Trigger Menu To selectively store branch conditions (State only) To selectively store branch conditions (State only) Besides setting up your trigger levels to store anystate, no state, or some subset of states, you can also choose whether or not to store branch conditions.
Using the Trigger Menu To place the trigger in memory To place the trigger in memory In Automatic Acquisition Mode, the exact location of the trigger depends on the trigger specification but usually falls around the center. You can manually place it at the beginning, end, or anywhere else. In the Analyzer Trigger menu, select Acquisition Control.
Using the Trigger Menu To set the sampling rates (Timing only) To set the sampling rates (Timing only) A timing analyzer samples the data based on its own internal clock. A short sample period provides more detail about the device under test; a long sample period allows more time before memory is full.
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Using the Pattern Generator This chapter provides instructions for using the pattern generator to generate vectors and patterns for design and test environments. It also covers the pattern generator common menus, loading ASCII files, and the pattern generator probing system. This chapter covers: •...
Setting Up the Proper Configurations This section discusses setting up the configuration attributes and parameters of the pattern generator. If you are reloading existing configurations or downloading ASCII vector files, refer to the Load operation in the disk drive menus of the System.
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Using the Pattern Generator To set up the configuration Set the Clock Period for an internal clock or the Clock Frequency for an external clock. The external clock frequency information is required to select the appropriate operating mode. Operating the pattern generator at an external clock frequency higher than selected will result in erroneous operation.
Using the Pattern Generator To build a label To build a label When you build a label, you are grouping channels under a label name and mapping the selected channels to the probes on the associated pods. A label may contain a maximum of 32 channels, however, a single channel cannot be used under more than one label.
Building Test Vectors and Macros Once the pattern generator is configured, you will want to build programs to use in your test system. You build programs in the Sequence menu. If you have small program segments that are built from frequently used vectors, they can be built in the User Macros Sequence menu.
Using the Pattern Generator To build a main vector sequence To build a main vector sequence During a single run, the program vectors in the MAIN SEQUENCE are output to the system under test in an order of first vector to last vector. The data of the last vector is then held until run is selected again.
Using the Pattern Generator To build an initialization sequence To build an initialization sequence Use the INIT SEQUENCE to place the system under test into a known initialization state. Default start and end program vectors are marked INIT SEQUENCE START and INIT SEQUENCE END. During a repetitive run, the initialization sequence is only executed the first time the program is run.
Using the Pattern Generator To include hardware instructions in a sequence To include hardware instructions in a sequence The following hardware instruction types are available: • Break • Signal IMB • Wait Event • If Event Highlight the vector that you want to output as a hardware instruction.
Using the Pattern Generator To include software instructions in a sequence To include software instructions in a sequence The following software instructions are available: • User Macro • Repeat Loop If you are inserting a User Macro and have not yet built the macro, go to "To build a user macro"...
Using the Pattern Generator To include a user macro in a sequence To include a user macro in a sequence If you have user macros, you can include them in the vector sequence using the following procedure. (If you have not yet built user macros, turn to "To build a user macro"...
Using the Pattern Generator To build a user macro To build a user macro Build macros for sequences of vectors you will want to use in multiple places. You can then insert these macros in INIT or MAIN sequences. Give each macro a name that will help you identify its function and make it easier to select from the list of macros you’ve built.
Using the Pattern Generator To modify a macro name To modify a macro name If you rename a macro, the new macro name will be displayed in INIT and MAIN sequences where the macro has been used. Select the macro to be renamed from the list of macros. Highlight the first line of the macro, then select the field.
Using the Pattern Generator To add, delete, or rename parameters To add, delete, or rename parameters Parameters are set when they are inserted into MAIN or INIT sequences. The changes you make in the parameter list will appear every place in the INIT or MAIN sequences in which you have used that macro.
Using the Pattern Generator To place parameters in a vector To place parameters in a vector Once parameters are added to the parameter list, you insert them into data fields in macro vectors. From the User Macro menu, select the desired data field in a vector. Select the Set Param field.
Using the Pattern Generator To enter or modify parameters To enter or modify parameters Each time you include a macro in an initialization or main sequence, you should enter the parameters for that particular instance. To enter or modify macro parameters, use the following procedure. From the Sequence menu, highlight the line which contains the macro name, then select the field.
Using the Pattern Generator To build a User Symbol Table To build a User Symbol Table You may want to build a symbol table to make inserting values into your program easier. You can name a symbol for one value in a label and insert that symbol into your vector sequence where you need it.
Using the Pattern Generator To include symbols in a sequence To include symbols in a sequence Symbols must be created before they become available for insertion. See the task on the preceding page for more information. From the Sequence menu, select the Base field under the desired label where you want a symbol used.
Using the Pattern Generator To include symbols in a macro To include symbols in a macro In the Format menu, you assign symbols to data under a given label. Once assigned, these symbols can be included under the same label in a macro. From the User Macros menu, select the label Base field for any label that has pre-assigned symbols.
Using the Pattern Generator To store a configuration To store a configuration Once you have completed configuring the pattern generator, you can save that configuration to hard disk for future uses. From the System menu, select Configuration. Select Hard Disk. Select the Store operation, then Patt Gen.
Using the Pattern Generator To load a configuration To load a configuration From the System menu, select Configuration. Select Hard Disk. Select the Load operation, then Patt Gen. Highlight the file to be loaded by rotating the knob. Select Execute. 5–21...
Using the Pattern Generator To use Autoroll To use Autoroll When Autoroll is used, each time you complete the process of adding data to a data field, the data entry focus changes to the next specified data field. The data entry keypad remains active, ready to define the next data field. The following procedure shows you how to use Autoroll: Select the first data field to define.
Pattern Generator Common Menus The Format Menu The Format menu lets you configure the pattern generator with a clock source and parameters, generate a symbol table, select its output mode, assign which vector output channels are used, and then group and label the vector output channels.
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• Less than 50 MHz • Between 50 MHz and 100 MHz • Greater than 100 MHz If the external clock is faster than the frequency range selected, the HP 1660CP will produce erroneous output vectors. 5–24...
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Using the Pattern Generator The Format Menu Clock Out Delay The Clock Out Delay setting allows you to position the output clock with respect to data. The zero setting is uncalibrated and should be measured to determine the initial position with respect to the data. Each numerical change of one on the counter results in an approximate change of 1.3 ns.
Using the Pattern Generator The Sequence Menu The Sequence Menu Use the Sequence menu to build your test vector files. There are two sequences, an initialization sequence and a main sequence. In single run mode, the vectors are output from the first vector in the initialization sequence to the last vector of the main sequence.
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Using the Pattern Generator The Sequence Menu INIT and MAIN Sequences Use the knob to highlight individual lines in either vector sequences. When a line is highlighted, you can add data lines below it by selecting the Insert field. Selecting the INST field brings up a dialog box that lets you insert one of the instructions or user macros into the vector sequence.
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Using the Pattern Generator The Sequence Menu Step Use the Step field to step through your vector sequence to debug a critical set of vectors following a break instruction in the program sequence. Stepping will begin at the vector following the break instruction, or the Output First State item can be pressed which will place the first vector of the sequence on the outputs.
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Using the Pattern Generator The Sequence Menu When deleting vector rows, the INIT START, INIT END, MAIN START, and MAIN END cannot be deleted. Deleting all the vector rows from INIT START to MAIN END will reset the sequence to the powerup state. The deletion will not be performed if the results of the delete operation will place fewer than two vectors in the main sequence, or, if the delete operation will place an instruction on any of the following vectors:...
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Using the Pattern Generator The Sequence Menu Merge is not allowed in the following cases: • Within a repeat loop. • Within an IF block (starting with the vector prior to the if, and ending with the vector following the IF). •...
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This also includes the Wait event. Signal IMB The Signal IMB instruction creates a signal for the IMB bus of the HP 1660CP at the current vector, allowing the pattern generator to trigger the state or timing analyzers. Multiple signal IMB instructions may be placed in the sequence, but only the first signal IMB will be executed.
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Using the Pattern Generator The Sequence Menu Wait Event The Wait Event instruction halts the execution of the program sequence until the event is received by the hardware. Selecting this instruction brings up a pop-up menu that lets you set four data patterns and select one of them or an IMB signal as the event the pattern generator is waiting for.
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Using the Pattern Generator The Sequence Menu Data Field Selecting the data field to the right of the instruction field lets you insert vector data. ASCII-based data cannot be edited, and ASCII- and Symbols-based data cannot be autorolled. Data Field The Sequence Menu with the Data Field Called Out Autoroll The Autoroll field is provided to reduce the number of keystrokes required to...
Using the Pattern Generator The User Macros Menu The User Macros Menu The User Macros menu is used to create new macros and edit existing macros. Macro 0 is the default macro and always exists. Macros let you define a pattern sequence once, then insert the macro by name wherever it is needed.
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Using the Pattern Generator The User Macros Menu Add/Delete Macro Selecting this field brings up a pop-up menu that lets you choose between adding a new macro or deleting one. If you select Add Macro, a new blank macro appears in the display with a new Macro "n" name. To rename the new macro, select the macro name field, and in the pop-up menu that appears, type in a new name.
Loading ASCII Files You can create pattern generator files and load them as ASCII files using one of the remote communication interfaces or by loading an ASCII disk file. Regardless of the load method selected, the general format of the file must conform to certain guidelines.
ASCII File Commands In addition to the unique ASCII file commands described here, you may want to include some standard FORMat commands in the ASCII file, such as those that are used to specify the clock or output mode. The only FORMat commands that are permitted are FORMat: MODe, CLOCk, and DELay.
Using the Pattern Generator LABel LABel Command LABel <name_str>,<width> label string, six characters maximum in length. <name_str> integer number of bits in the label (1 through 32). <width> The LABel command is a special means of specifying labels for use by an ASCII file.
If the actual data count is less than the data count passed in with the VECTor command, the bus transfer will appear to hang while the HP 1660CP system waits for the ’remaining’ data. The controller sending the file may, or may not, time-out and terminate the bus transfer.
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Using the Pattern Generator VECTor No data is allowed in the same line as the VECTor command. The line termination in the VECTor command line is included in the character count for the file. The <char_count> field is not required as part of the VECTor command when creating a disk file, and will be ignored if included.
This <lf> is NOT included in the <char_count> value. It is required to ensure the data buffer is flushed. Serious problems will cause the default main program to be loaded in an effort to avoid locking up the HP 1660CP system. FORMat:xxx Command...
Using the Pattern Generator Loading an ASCII file over a bus (example) Loading an ASCII file over a bus (example) To load an ASCII file over the bus use the following example. A few items to be noted: • Line numbers are added for documentation only and are NOT part of the actual remote bus commands.
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Using the Pattern Generator Loading an ASCII file over a bus (example) • There is a space before the ’#8’ in line 050. • The character count in line 050 is based on: • 15 characters (10 digits, 4 blanks, 1 <lf>) each in lines 060, 080, 100, 110, and 120 •...
Pattern Generator Probing System This section discusses the probing system for the Pattern Generator. Pod Numbering The HP 1660CP pods are numbered as shown in the figure below. HP 1660CP Pattern Generator Pods 5–44...
Using the Pattern Generator Connecting Pods Directly to a PC Board Connecting Pods Directly to a PC Board To connect the pattern generator pods directly to the PC board, use one of the following two methods. Both methods require that a 3M 2520-series, or similar alternative connector be installed on the PC board.
Skew Typical <2 ns; worst case 4 ns (see note 1) Recommended lead set HP 10474A HP 10462A 3-State TTL/CMOS Data Pod Output type 74ACT11244 with 100 ohm in series 10H125 on non 3-state channel 7 (see note 2), 3-state enable...
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Skew Typical <1 ns; worst case 2 ns (see note 1) Recommended lead set HP 10347A HP 10466A 3-State TTL/3.3 Volt Data Pod Output type 74LVT244 with 100 ohm in series 10H125 on non 3-state channel 7 (see note 2)
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3-state enable. Data Cable Characteristics Without a Data Pod The HP 1660CP data cables without a data pod provide an ECL-terminated (1 KΩ to -5.2 V) differential signal. These are usable when received by a differential receiver, preferably with a 100-ohm termination across the lines.
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Using the Pattern Generator Output Pod Characteristics HP 10460A TTL Clock Pod Clock output type 10H125 with 47 ohm series; true & inverted Clock output rate 100 MHz maximum Clock out delay 11 ns maximum in 9 steps Clock input type...
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Triggering Examples As you begin to understand a problem in your system, you may realize that certain conditions must occur before the problem occurs. You can use sequential triggering to ensure that those conditions have occurred before the analyzer recognizes its trigger and captures information.
Single-Machine Trigger Examples The following examples require only a single analyzer to make measurements. Sequence specifications are given in the form you see within the sequence levels, but the illustrations show the complete, multi-level sequence specification. Although all the examples are case-specific, terms are named in a way that highlights their role in solving the trigger problem.
Single-Machine Trigger Examples To store and time the execution of a subroutine To store and time the execution of a subroutine Most system software of any kind is composed of a hierarchy of functions and procedures. During integration, testing, and performance evaluation, you want to look at specific procedures to verify that they are executing correctly and that the implementation is efficient.
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Single-Machine Trigger Examples To store and time the execution of a subroutine The figure below shows what you would see on your analyzer screen after entering the sequence specification given in step 4. Trigger Setup for Storing and Timing Execution of a Subroutine Suppose you want to trigger on entry to a routine called MY_SUB.
Single-Machine Trigger Examples To trigger on the nth iteration of a loop To trigger on the nth iteration of a loop Traditional debugging requires print statements around the area of interest. This is not possible in most embedded systems designs, but the analyzer lets you view the system’s behavior when a particular event occurs.
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Single-Machine Trigger Examples To trigger on the nth iteration of a loop The specification has some advantages and a potential problem. • The advantages are that a pipelined processor won’t trigger until it has executed the loop 10 times. Requiring LP_END to be seen at least once first ensures that the processor actually entered the loop;...
Single-Machine Trigger Examples To trigger on the nth recursive call of a recursive function To trigger on the nth recursive call of a recursive function Go to the state analyzer’s Trigger menu. Define the terms CALL_ADD, F_START, and F_END to represent the called address of the recursive function, and the start and end addresses of the function.
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Single-Machine Trigger Examples To trigger on the nth recursive call of a recursive function Triggering on the 10th Call of a Recursive Function...
Single-Machine Trigger Examples To trigger on entry to a function To trigger on entry to a function This sequence triggers on entry to a function only when it is called by one particular function. Go to the state analyzer’s Trigger menu. Define the terms F1_START and F1_END to represent the start and end addresses of the calling function.
Single-Machine Trigger Examples To capture a write of known bad data to a particular variable To capture a write of known bad data to a particular variable The trigger specification ANDs the bad data on the data bus, the write transaction on the status bus, and the address of the variable on the address bus.
Single-Machine Trigger Examples To trigger on a loop that occasionally runs too long To trigger on a loop that occasionally runs too long This example assumes the loop normally executes in 14 µs. Go to the state analyzer’s Trigger menu. Define terms LP_START and LP_END to represent the start and end addresses of the loop, and set Timer1 to the normal duration of the loop.
Single-Machine Trigger Examples To verify correct return from a function call To verify correct return from a function call The exit code for a function will often contain instructions for deallocating stack storage for local variables and restoring registers that were saved during the function call.
Single-Machine Trigger Examples To trigger after all status bus lines finish transitioning To trigger after all status bus lines finish transitioning In some applications, you will want to trigger a measurement when a particular pattern has become stable. For example, you might want to trigger the analyzer when a microprocessor’s status bus has become stable during the bus cycle.
Single-Machine Trigger Examples To find the nth assertion of a chip select line To find the nth assertion of a chip select line Go to the timing analyzer’s Trigger menu. Define the Edge1 term to represent the asserting transition on the chip select line.
Single-Machine Trigger Examples To verify that the chip select line is strobed after the address is stable To verify that the chip select line is strobed after the address is stable Go to the timing analyzer’s Trigger menu. Define a term called ADDRESS to represent the address in question and the Edge1 term to represent the asserting transition on the chip select line.
Single-Machine Trigger Examples To trigger when expected data does not appear when requested To trigger when expected data does not appear when requested Go to the timing analyzer’s Trigger menu. Define a term called DATA to represent the expected data, the Edge1 term to represent the chip select line of the remote device, and the Timer1 term to identify the time limit for receiving expected data.
Single-Machine Trigger Examples To test minimum and maximum pulse limits To test minimum and maximum pulse limits Go to the timing analyzer’s Trigger menu. Define the Edge1 term to represent the positive-going transition, and define the Edge2 term to represent the negative-going transition on the line with the pulse to be tested.
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Single-Machine Trigger Examples To test minimum and maximum pulse limits Triggering when a Pulse Exceeds Minimum or Maximum Limits 6-19...
Single-Machine Trigger Examples To detect a handshake violation To detect a handshake violation Go to the timing analyzer’s Trigger menu. Define the Edge1 term to represent either transition on the first handshake line, and the Edge2 term to represent either transition on the second handshake line.
Single-Machine Trigger Examples To detect bus contention To detect bus contention In this setup, the trigger occurs only if both devices assert their bus transfer acknowledge lines at the same time. Go to the timing analyzer’s Trigger menu. Define the Edge1 term to represent assertion of the bus transfer acknowledge line of one device, and Edge2 term to represent assertion of the bus transfer acknowledge line of the other device.
Cross-Arming Trigger Examples The following examples use cross arming to coordinate measurements between two separate analyzers within the logic analyzer or between analyzers and the pattern generator. The analyzers can be configured as either a state analyzer and timing analyzer, or two state analyzers. It is not possible to set both to timing.
Cross-Arming Trigger Examples To examine software execution when a timing violation occurs To examine software execution when a timing violation occurs The timing analyzer triggers when the timing violation occurs. When it triggers, it also sets its "arm" level to true. When the state analyzer receives the arm signal, it triggers immediately on the present state.
Cross-Arming Trigger Examples To look at control and status signals during execution of a routine To look at control and status signals during execution of a routine The state analyzer will trigger on the start of the routine whose control and status signals are to be examined more frequently than once per bus cycle.
Cross-Arming Trigger Examples To detect a glitch To detect a glitch The following setup uses a state analyzer to capture state flow occurring at the time of the glitch. This can be useful in troubleshooting. For example, you might find that the glitch is ground bounce caused by a number of simultaneous signal transitions.
Cross-Arming Trigger Examples To trigger timing analysis of a count-down on a set of data lines To trigger timing analysis of a count-down on a set of data lines Your target system may include various state machines that are started by system events such as interrupt processing or I/O activity.
Cross-Arming Trigger Examples To monitor two coprocessors in a target system To monitor two coprocessors in a target system Debugging coprocessor systems can be a complex task. Replicated systems and contention for shared resources increase the potential problems. Using two state analyzers with preprocessors can make it much easier to discover the source of such problems.
Special Displays Interleaved trace lists Interleaved trace lists allow you to view data captured by two analyzers in a single display. When you interleave the traces, you see each state that was captured by each analyzer. These states are shown on consecutive lines. You can interleave state listings from state analyzers when two are used together in a run.
If you have problems with the procedure, check that each analyzer has an independent clock from the target system. Interleaved Trace Lists on the HP 1661CP 6-29...
Special Displays To view trace lists and waveforms on the same display To view trace lists and waveforms on the same display Set up a timing and a state analyzer. Go to the state analyzer’s Trigger menu. Set Count to Time, and set up the trigger as appropriate. You do not need to have one instrument arming the other to display the information jointly, but you do need to turn on Count Time so that the information may be correlated.
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Special Displays To view trace lists and waveforms on the same display Mixed Display using Timing and State in the HP 1661CP 6-31...
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The examples store files on the flexible disk drive, but you can move the same files to your host computer using a network interface. The HP 1660CP family of logic analyzers have HP-IB and RS-232-C capabilities, and an ethernet interface. If you need help using the LAN interface, see the LAN User’s Guide.
Transferring Files Using the Flexible Disk Drive Because the flexible disk drive on the HP 1660CP-series logic analyzer will read and write double-sided, double-density, or high-density disks in MS-DOS format, it is a useful tool for transferring data to and from IBM PC-compatible computers as well as transferring data to and from other systems that can read and write MS-DOS format.
File Management To save a configuration To save a configuration You can save configurations on a 3.5-inch disk or on the internal hard disk for later use. This is especially useful for automating repetitive measurements for production testing. Go to the System Hard Disk or System Flexible Disk menu. Set the field under System to Store.
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File Management To save a configuration Saving the System Configuration for Programmatic Control...
File Management To load a configuration To load a configuration You can quickly load a previously saved configuration, so that you will not have to manually set up the measurement parameters. Go to the System Hard Disk or System Flexible Disk menu. Your choice here depends on where you saved the configuration.
File Management To save a trace list in ASCII format To save a trace list in ASCII format Some screens, such as file lists and trace lists, contain columns of ASCII data that you may want to move to a computer for further manipulation or analysis.
File Management To save a screen’s image To save a screen’s image You can save menus and measurements to disk in one of four different graphical formats. Insert a formatted flexible disk in the flexible disk drive. Set up the menu whose image you want to capture, or run a measurement from which you want to save data.
To load additional software To load additional software You can enhance the power of your HP 1660CP-series logic analyzer by installing software such as symbol utilities. The software comes with installation instructions. In general, however, you can install logic analyzer software by following these instructions.
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Logic Analyzer Description The HP 1660CP-series logic analyzers are part of a family of general- purpose logic analyzers. The HP 1660CP-series consists of four models ranging in channel width from 34 channels to 136 channels, with 100-MHz state and 500-MHz timing speeds and a 200 M Vector/s pattern generator.
Configuration Capabilities The four analyzer models in the HP 1660CP-series offer a wide variety of channel widths and memory depth combinations. The number of data channels range from 34 channels with the HP 1663CP, to a maximum of 136 channels with the HP 1660CP. In addition, a...
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Configuration Capabilities Table 8-2 Timing Analyzer Configurations Mode HP 1660CP HP 1661CP HP 1662CP HP 1663CP Conventional 8K-deep / 68 8K-deep / 51 8K-deep / 34 8K-deep / 17 half-channel chan. 65 data chan. 48 data chan. 32 data chan. 16 data...
Standard general-purpose probing (provided). • Direct connection to a 20-pin, 3M-Series type header connector using the optional termination adapter. Accessories for HP Logic Analyzers for additional information about See Also the microprocessor interface kits and for any new probing solutions.
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Bus interfaces will support bus analysis for the following: • Bus support for HP-IB, RS-232-C, RS-449, SCSI, VME, and VXI. General-Purpose Probing General-purpose probing connects the logic analyzer probes directly to your target system without using any interface. General-purpose probing does not limit you to specific hookup schemes.
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Probing The Termination Adapter The logic analyzer must be properly terminated to operate correctly. Most HP preprocessor interfaces have properly terminated state connectors; however, many of them require termination adapters for the timing connectors. The optional termination adapter lets you connect the logic analyzer probe cables directly to test ports on your target system without the probes.
Probing General-purpose probing system description General-purpose probing system description The standard probing system provided with the logic analyzer consists of a probe tip assembly, probe cable, and grabbers. Because of the passive design of the probes, there are no active circuits at the outer end of the cable. The rest of this chapter is dedicated to general-purpose probing.
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Probing General-purpose probing system description Probe and Pod Grounding Each pod is grounded by a long, black, pod ground lead. You can connect the ground lead directly to a ground pin on your target system or use a grabber. To connect the ground lead to grounded pins on your target system, you must use 0.63-mm (0.025-in) square pins, or use round pins with a diameter of 0.66 mm (0.026 in) to 0.84 mm (0.033 in).
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Probing General-purpose probing system description Grabbers The grabbers have a small hook that fits around the IC pins and component leads. The grabbers have been designed to fit on adjacent IC pins on either through-hole or surface-mount components with lead spacing greater than or equal to 0.050 inches.
Probing Assembling the probing system Assembling the probing system The general-purpose probing system components are assembled as shown to make a connection between the measured signal line and the pods displayed in the Analyzer Format menu. Connecting Probe Cables to the Logic Analyzer 8-11...
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All probe cables are installed at Hewlett-Packard. If you need to replace a probe cable, refer to the HP 1660C/CS/CP-Series Logic Analyzers Service Guide. You can purchase the Service Guide from your HP Sales Office. Connecting the Probe Tip Assembly to the Probe Cable To connect a probe tip assembly to a cable, align the key on the cable connector with the slot on the probe housing and press them together.
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Probing Assembling the probing system Disconnecting Probe Leads from Probe Tip Assemblies When you receive the logic analyzer, the probe leads are already installed in the probe tip assemblies. To keep unused probe leads out of your way during a measurement, you can disconnect them from the pod. To disconnect a probe lead, insert the tip of a ballpoint pen into the latch opening.
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Probing Assembling the probing system Connecting the Grabbers to the Probes Connect the grabbers to the probe leads by slipping the connector at the end of the probe onto the recessed pin located in the side of the grabber. If you need to use grabbers for either the pod or the probe grounds, connect the grabbers to the ground leads in the same manner.
Keyboard Shortcuts This section explains how to use the optional keyboard interface (HP E2427B Keyboard Kit). You can use the keyboard interchangeably with the knob and front-panel keypad for all menu applications. The keyboard functions fall into the two basic categories of cursor movement and data entry.
Pressing either the Return key or the Enter key will terminate data entry for that item. Using the keyboard overlays A keyboard overlay is included in the HP E2427B Keyboard Kit. The table below represents the key mappings. Functions Like...
Common Menu Fields There are a number of fields that appear throughout the different menus that have similar operation. These common fields are listed below: • Mode (System/Analyzer) field • Menu field • Print field • Run field • Base field •...
Common Menu Fields Print field Print field The Print field prints what is displayed on the screen at the time you initiate the printout. When you select the Print field, a print selection pop-up appears showing you one or more of the following options: •...
Common Menu Fields Run/Stop field Print All The Print All option prints not only what is displayed on the screen, but data that is below the screen. This option is only available when an ASCII form of the screen is possible. For example, Print All is never available in Waveform. When you select Print All with a Listing menu, make sure the first line you want to print is in the state location box (also referred to as the data roll field) at the center of the listing area.
Common Menu Fields Roll fields Roll fields Some data may not fit on screen when there are many pods or labels to display. When this happens, it is indicated by the Label/Base field becoming selectable and its shade changing to the common field shade. To move through the hidden data, select the field, wait for the roll indicator to appear, and then use the knob to move through the data.
Disk Drive Operations The logic analyzer has a built-in 3.5-inch, double-sided, high-density or double-density, flexible disk drive. The disk drive is compatible with both LIF (Logical Interchange Format) and DOS (Disk Operating System) formats. It also has an internal hard disk drive, which performs the same operations as the flexible disk drive.
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Disk Drive Operations Disk operations • Load Loads a file into the logic analyzer, overwriting the current settings or information. You can load system configurations, analyzer measurement setups including measurement data, and inverse assembler files. • Make Directory Creates a new directory on a DOS disk. You can save or copy files to the new directory using the store and copy commands.
Disk Drive Operations Autoload Autoload The Autoload operation allows you to designate a set of configuration files to be loaded automatically the next time the analyzer is turned on. This allows you to change the default configuration of certain features to one that better fits your needs.
System files store system configurations. System information for the HP 1660CP-series consists of settings for printer, controller, RS-232-C, HP-IB, shade, and sound. LAN settings are not saved. System configuration files end in two underscores and have a file type of 16[6/7]x_cnfg.
Controller interface The logic analyzer is equipped with a standard RS-232-C interface and an HP-IB interface that allow you to connect to a controller. Either interface gives you remote access for running measurements, for uploading and downloading configurations and data, and connecting to printers. If you purchased the optional Ethernet LAN interface, it can also be used for controlling the logic analyzer.
HP-IB interface setting configurable from the logic analyzer. The HP-IB address can be set to 31 different HP-IB addresses, from 0 to 30. Simply choose a compatible address for your device and software. The default address for all HP logic analyzers is 7. In the System External I/O menu, select HP-IB Settings and then set the Address field to your address.
With a full 5-wire interface, selecting None allows a hardware handshake to occur. With a hardware handshake, hardware signals control data flow. The HP 13242G cable allows the logic analyzer to support hardware handshake. The Centronics interface The Centronics interface is an industry-standard parallel printer interface.
System Utilities The System Utilities menu is used for setting system level parameters such as the system clock, display intensity for each shade, and the sound. In this menu you can also rewrite the analyzer’s memory with any new revisions of the operating system. Real Time Clock Adjustments field A real-time clock is displayed in the Waveform and Listing menus.
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System Utilities Update FLASH ROM field The analyzer warns, "Selecting Continue Will Erase & Update Flash ROMs." and waits for you to select Cancel or Continue. If you select Continue, the analyzer will be reset. If you need to save the measurement data, select Cancel.
System Utilities Shade adjustments Shade adjustments You can adjust the greys of the display to different levels of intensity. Select the shade number, then select luminosity and adjust it with the knob. Default Shades restores all shade intensity levels to the original factory settings. 8-30...
The Analyzer Configuration Menu Type field The Type field lets you configure the logic analyzer with either an internal clock (Timing mode) or an external clock (State and SPA). When the Type field is selected, the following choices are available. Timing When Timing is selected, the analyzer uses its own internal clock to clock measurement data into the acquisition memory.
The Analyzer Format Menu Pod threshold field The Analyzer Format Menu Pod threshold field The pod threshold field is used to set a voltage level that the data must reach before the analyzer recognizes and displays it as a change in logic levels. Threshold levels apply to single pods, and cover both data and clock channels.
The Analyzer Format Menu State acquisition modes (state only) State acquisition modes (state only) The State Acquisition Mode field identifies the channel width and memory depth of the selected acquisition mode. There are two configurations of channel width/memory depth. Full Channel/4K Memory/100 MHz Full-channel mode uses both pods in a pod pair for 34 channels of width and a total memory depth of 4 K per channel.
The Analyzer Format Menu Timing acquisition modes (timing only) Timing acquisition modes (timing only) The Timing Acquisition mode field identifies the acquisition type, the channel width, and sampling speed of the present acquisition mode. There are three acquisition modes and five configurations. Conventional Acquisition Mode In Conventional Acquisition mode, the analyzer stores measurement data at each sampling interval.
1/2, the L and M with pod pair 3/4, and N and P with pod pairs 7/8 for the HP 1660 and 5/6 for the HP 1661. In a model with more than three pod pairs, all other clock lines are displayed to the left of the displayed master clocks, and are used only as data channels.
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The Analyzer Format Menu Pod clock field (State only) Master This option specifies that data on all pods designated "Master Clock," in the same analyzer, are strobed into memory when the status of the clock lines match the clocking arrangement specified under the Master Clock. See Also "Master and Slave Clock fields (State only)"...
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The Analyzer Format Menu Pod clock field (State only) Channel assignments are displayed as Demux Master and Demux Slave. For easy recognition of the two sets of data, assign slave and master data to separate labels. When the analyzer sees a match between the slave clock input and the Slave Clock arrangement, Demux Slave data is latched.
The Analyzer Format Menu Master and Slave Clock fields (State only) Master and Slave Clock fields (State only) The Master and Slave Clock fields are used to construct a clocking arrangement. A clocking arrangement is the assignment of appropriate clocks, clock edges, and clock qualifier levels which allow the analyzer to synchronize itself on valid data.
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The Analyzer Format Menu Master and Slave Clock fields (State only) Clock edges are ORed to clock edges, clock qualifiers are ANDed to clock edges, and clock qualifiers can be either ANDed or ORed together. All clock and qualifier combinations on the left side of the graphic line are ORed to all combinations on the right side of the line.
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The Analyzer Format Menu Master and Slave Clock fields (State only) Setup/Hold field Setup/Hold in the Master and Slave Clock fields adjusts the relative position of the clock edge with respect to the time period that data is valid. When the Setup/Hold field is selected, a configuration menu appears.
When measurements are made, the mnemonic is displayed where the bit pattern occurs using the selected symbol base. You can also download compiled symbol tables using HP E2450A Symbol Utility, which is supplied with the logic analyzer. See Also HP E2450A Symbol Utility User’s Guide for more information on...
The Analyzer Format Menu Label fields Symbol Width field The Symbol Width field specifies how many characters of the symbol name will be displayed when the symbol is referenced in the Trigger, Waveform, and Listing menus. You can display from 1 to 16 characters of the symbol name.
The Analyzer Format Menu Label polarity fields Channels assigned to a label are numbered from right to left by the logic analyzer. The least significant assigned channel on the far right is numbered 0, the next assigned channel is numbered 1, and all other channels are assigned sequentially up to the maximum of 16 per pod.
The Analyzer Trigger Menu Trigger sequence levels Sequence levels are the definable stages of the total trigger specification. Individual sequence levels are assigned using either a predefined trigger macro or a user-level trigger macro. The total trigger specification can contain both kinds of macro. See Also Chapter 4, "Using the Trigger Menu,"...
The Analyzer Trigger Menu Timing trigger macro library When the macro is in a broken-down form, you can change the structure. However, when the macros are restored, all changes are lost and any branching that is part of the original structure is restored. Use Break Down Macros if you want to view a particular macro part in its long form to see the exact sequence flow.
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The Analyzer Trigger Menu Timing trigger macro library This macro becomes true when the designated edge is seen. It uses one internal sequence level. 5. Find Nth occurrence of an edge This macro becomes true when it finds the designated occurrence of a designated edge.
The Analyzer Trigger Menu State trigger macro library 3. Find width violation on a pattern/pulse This macro becomes true when the width of a pattern violates designated minimum and maximum width settings. It uses four or five internal sequence levels. •...
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The Analyzer Trigger Menu State trigger macro library Sequence 1. Find event 2 "n" times after event 1 before event 3 occurs Dependent macros This macro becomes true when it first finds a designated pattern 1, followed by a selected number of occurrences of a designated pattern 2. In addition, if a designated pattern 3 is seen anytime while the sequence is not yet true, the sequence starts over.
The Analyzer Trigger Menu Modifying the user macro Modifying the user macro Before you begin building a trigger specification using the user macro, it should be noted that in most cases one of the predefined trigger macros will work. If you need to accommodate a specific trigger condition, or you prefer to construct a trigger specification from scratch, use the User macro as a starting point.
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The Analyzer Trigger Menu Modifying the user macro Using bit patterns, ranges, and edges Bit patterns are set to match specific data values, and ranges are set to match a range of bit patterns. In the Timing Acquisition mode, edges are set to match specific edges of a timing pulse.
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The Analyzer Trigger Menu Modifying the user macro As more sequence levels are added, the timer status in the new levels defaults to Off. Timers must be continued or started in each new level as appropriate. When a timer expires or stops, its count resets to zero. Branching If either the less than or greater than duration is used, only the primary branch is available.
The Analyzer Trigger Menu Resource terms Resource terms Resource terms are user-defined variables that are assigned to sequence levels. They are placed into the sequence statement where their bit pattern or edge type is searched for within the data stream. When a match is found, a branch is initiated and the next statement or sequence level is acted upon.
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The Analyzer Trigger Menu Resource terms Global timers 1 and 2 In addition to the resource terms available, there are two global timers available. Each timer can be started, paused, continued, or stopped from any sequence level except the first. Assigning resource term names and values The Terms field identifies the list of available resource terms within the analyzer.
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The Analyzer Trigger Menu Resource terms Assigning Bit by Bit Bit pattern terms Just to the right of the bit pattern name fields are the term assignment fields. When any of the individual assignment fields are selected, a keypad appears. Use this keypad to assign real values or Don’t Care (X) values.
The Analyzer Trigger Menu Arming Control field Arming Control field Arming Control sets up the order of triggering for complicated measurements involving more than one machine. You can set the logic analyzer to begin running when it receives a signal from an external machine, have one analyzer start the other, or have one analyzer send a signal to another external machine.
The Analyzer Trigger Menu Acquisition Control field Acquisition Control field Selecting the Acquisition Control field pops up the Acquisition Control menu. The Acquisition Control menu sets the acquisition mode, the trigger position within acquisition memory, and the sample period. Acquisition Mode field The Acquisition Mode field toggles between Manual and Automatic.
The Analyzer Trigger Menu Count field (State only) data values that caused the branch are stored. When the analyzer is set to Branches Taken Not Stored, only the data you explicitly designate in the sequence levels is stored. The Branches Taken Stored/Not Stored is not available when the analyzer is configured as a timing analyzer.
The Listing Menu Markers The Markers field accesses the markers selection menu. When the Markers field is selected, a marker selection menu appears with the marker choices appropriate for the present analyzer configuration. The Off selection turns off marker operations but does not turn off operations based on the markers.
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The Listing Menu Markers Off The Off selection turns all Stop measurement operations off. If the stop measurement operation is not turned off and the stop measurement criteria is met, the measurement will stop even though the markers are set to other types or turned off. X-O The X-O option is available in the Timing analyzer and in the State analyzer with its count set to Time.
The Waveform Menu sec/Div field When acquisition control is set to automatic, the sec/Div field affects the sample period. Timing waveforms are reconstructed relative to the sample period. A shorter sample period puts more sample points on the waveform for a more accurate reconstruction but also fills memory more quickly. If the sec/Div is changed resulting in a change in the next sample period, you must run the analyzer again before the current sample period display is updated.
The Waveform Menu Waveform label field The delay range of a timing analyzer is from −2500 seconds to +2500 seconds. The delay range of a state analyzer is from −8192 states to +8192 states. Waveform label field The waveform label field, located on the left side of the waveform display, is both a display and configuration field.
The Waveform Menu Waveform display Waveform display At the bottom of the Waveform menu is a reference line which displays the relative location of the display window, the markers, and the trigger point with reference to the total memory. Total memory is represented by a horizontal dotted line. The display window is represented by an overlaid solid line.
The Mixed Display Menu The Mixed Display menu combines a state listing display located at the top of the menu and a waveform display located at the bottom of the menu. The Mixed Display menu shows both state and timing data in the same display. The Mixed Display menu only becomes available when at least one analyzer is configured as a state analyzer, with its Count field in the Trigger menu set to Time.
The Mixed Display Menu Time-correlated displays Time-correlated displays Once the Time markers are set in the Waveform display area of the Mixed Display menu, time-correlated X and O Time markers will be displayed in both the listing and the waveform display areas. Markers The markers in the Mixed Display menu are not the same as the markers in the individual Listing and Waveform menus.
The Chart Menu State Chart is a software post-processing feature that provides the ability to build x-y charts of label activity using state data. The Chart menu builds a graphical representation of the system under test. The Y axis always represents data values for a specified label. You can select whether the X axis represents states (rows in the state listing) or the data values for another label.
The Chart Menu Min and Max scaling fields Min and Max scaling fields When State is selected for the X axis, the minimum and maximum values can range from −8192 to +8192 depending on the trace point location. When Label is selected for either axis, the minimum and maximum values range from 00000000 hex to FFFFFFFF hex regardless of the axis, because labels are restricted to 32 bits.
The Compare Menu State Compare is a software postprocessing feature that compares bit-by-bit the acquired state data listing and a reference listing. State Compare is only available when at least one analyzer is configured as a State analyzer. The comparison between the acquired state listing data and the data in the reference listing is done relative to the trigger points.
The Compare Menu Reference Listing field Reference Listing field The Reference Listing field is a toggle field that switches the listing type between the Reference image listing and the Difference listing. The Reference listing is a display of the image (or template) that acquired data is compared to during a comparison measurement.
The Compare Menu Copy Listing to Reference field Copy Listing to Reference field The initial Reference image is generated by either copying the data listing from the listing menu or by loading an analyzer configuration file which contains a Reference listing. Be aware that if you load an analyzer configuration to get a Reference image, the other menu setups will change.
The Compare Menu Mask field Mask field The channel masking field is used to specify a bit, or bits in each label that you do not want compared. This causes the corresponding bits in all states to be ignored in the comparison. The Reference data image itself remains unchanged on the display.
State Histogram, and Time Interval modes. To be successful with this software, you should be familiar with the operation of the logic analyzer. The screen shots shown in this chapter are HP 16550A screens. This chapter is organized as follows: •...
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Error messages and warnings used by SPA are the same as those used by each of the logic analyzers. Refer to "Troubleshooting," Chapter 11, for descriptions of these messages. If you need programming information, refer to the HP 1660C/CS/CP-Series Logic Analyzers Programmer’s Guide, available from your HP Sales Office.
System Performance Analysis (SPA) Software What is System Performance Analysis? What is System Performance Analysis? The logic analyzer’s state or timing analyzer is used to make quantitative measurements on specific events in the target system. For example, they can measure a specific time interval on a microprocessor’s control lines or can find out how a particular subroutine was called.
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System Performance Analysis (SPA) Software What is System Performance Analysis? • The Y axis is the relative number of occurrences in each bucket. • The maximum value of the Y axis is constantly updated to reflect the number of occurrences in the bucket that has the most occurrences, and is displayed as "Max count".
System Performance Analysis (SPA) Software Getting started Getting started This section describes how to access the System Performance Analysis (SPA) menus. Also, it describes selecting the SPA modes and setting the specifications. Accessing the menus The SPA menus are accessed through the Analyzer Configuration menu. When the configuration menu is displayed, select the Type field and choose SPA from the pop-up.
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System Performance Analysis (SPA) Software Getting started Setting up the State Format specification When a State or Timing analyzer is changed to SPA, SPA will retain the State or Timing Format specification. For complete details on changing from a State or Timing Analyzer to SPA, see "Using SPA with other features." The State and Timing format specification menus provide symbol tables.
System Performance Analysis (SPA) Software SPA measurement processes SPA measurement processes This section introduces you to the measurement processes of the System Performance Analysis (SPA) software. It tells you how to select the appropriate trace mode and labels. It also explains how SPA samples and sorts data.
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System Performance Analysis (SPA) Software SPA measurement processes has been sorted, the histograms and displayed statistics are updated, and the analyzer is re-armed for the next acquisition. Refer to the following sections on the three trace modes for details on sorting criteria and statistical computation.
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System Performance Analysis (SPA) Software SPA measurement processes divided equally among 256 buckets. For example, if the range defined by the low and high values is 1100, then 1100 divided by 256 equals 4.29. This value will be rounded up to 5, each bucket will have a range of 5, and only 220 buckets will be used (1100/5 = 220).
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System Performance Analysis (SPA) Software SPA measurement processes Example State Overview example An example of a State Overview measurement is testing for access to a reserved area of memory. In this case, the address bus of the target system would need to be grouped under a single label, such as ADDR. By selecting the ADDR label in State Overview mode, and by defining the full range of the label (Low value = 0000, High value = FFFF with a 16-bit ADDR label), activity over the entire address range can be monitored.
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System Performance Analysis (SPA) Software SPA measurement processes State Histogram mode State Histogram mode displays relative activity of ranges of a specified label. The ranges can also be compared to activity on the rest of the label not defined in the ranges. Data qualification is possible with State Histogram, so data can be filtered during acquisition.
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System Performance Analysis (SPA) Software SPA measurement processes If a range has a low and high value and a name defined, and the range is turned off, it will retain the low and high value and name when turned back User-defined ranges vs.
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System Performance Analysis (SPA) Software SPA measurement processes Format Specification as a combination of values, in the current base, and don’t cares. For example, a microprocessor target system memory may contain two arrays. In State Histogram, the address ranges of the arrays can be defined and the relative activity in the arrays monitored.
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System Performance Analysis (SPA) Software SPA measurement processes Time Interval mode Time Interval mode shows distribution of the execution time of a single event. The event is defined by specifying Start and End conditions as patterns across all labels defined in the Format Specification. Data sampling and sorting When you press Run, the analyzer samples the target system using the definitions entered in the Format Specification.
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System Performance Analysis (SPA) Software SPA measurement processes ranges. The minimum allowable limit is 0 ns, the maximum 9,999,999 seconds. Ranges do not have to be contiguous. However, gaps between ranges increase the risk of missed data. If two ranges overlap, data will be counted in both ranges.
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System Performance Analysis (SPA) Software SPA measurement processes Example Time Interval example A team of applications programmers is writing a math package for a spreadsheet. They need to develop standards for the various math functions. Using time interval mode, they can test the execution time of each of the math functions.
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You connect the HP logic analyzer to the address bus of your system. In the Format Specification, you define a 32-bit label called ADDR and the state clocking.
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System Performance Analysis (SPA) Software SPA measurement processes Next, you go to the State Histogram menu and enter the names and boundaries of the five routines in the state histogram ranges. State Histogram then displays the relative activity of the five routines. After several acquisitions, it is apparent that the interrupt routine is being accessed more often than expected.
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System Performance Analysis (SPA) Software SPA measurement processes SPA Time Interval 9-20...
System Performance Analysis (SPA) Software Using State Overview, State Histogram, and Time Interval Using State Overview, State Histogram, and Time Interval This section explains how to select the display fields, set up the logic analyzer and use the State Overview, State Histogram and Time Interval modes of SPA.
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System Performance Analysis (SPA) Software Using State Overview, State Histogram, and Time Interval SPA State Overview Menu with Fields Called Out Specifying Low and High values The range of the X axis is determined by the Low value and High value fields (item 2 in figure above).
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System Performance Analysis (SPA) Software Using State Overview, State Histogram, and Time Interval Interpreting the histogram display Press the blue shift key and Run to start the State Overview acquisition. As the data is sampled and sorted, the buckets along the X axis will accumulate (item 3 in the figure on the previous page).
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System Performance Analysis (SPA) Software Using State Overview, State Histogram, and Time Interval Using State Histogram mode Choosing a label to monitor To specify a label to monitor, select the Label field in the State Histogram display (item 1 in the figure below). In the pop-up, you will see a list of all the labels defined in the Format specification.
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System Performance Analysis (SPA) Software Using State Overview, State Histogram, and Time Interval Using symbols for ranges In the Format menu, you can define symbols for any available label. The symbols can be defined as Pattern Symbols or Range Symbols. For complete information on defining and using symbols, see "Symbols field"...
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System Performance Analysis (SPA) Software Using State Overview, State Histogram, and Time Interval Interpreting the histogram display Press the blue shift key and Run to start the State Histogram acquisition. The relative activity over the ranges you defined is displayed as histograms (see the figure on the previous page).
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System Performance Analysis (SPA) Software Using State Overview, State Histogram, and Time Interval Using Time Interval mode Use Time Interval mode to determine the distribution of time between two specific events. The state analyzer uses the time tag feature to time the event;...
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System Performance Analysis (SPA) Software Using State Overview, State Histogram, and Time Interval Defining the Time Interval ranges Before changing the ranges from their default values, you may want to press Run and acquire some data. From this initial run, the Maximum (Max), Minimum (Min), and Average (Avg) statistics on the display will help you choose the appropriate set of Time Interval ranges.
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System Performance Analysis (SPA) Software Using State Overview, State Histogram, and Time Interval The analyzer continues to search for Start/End event pairs until you press Stop or change a display variable. The distribution of the events’ time duration is displayed as histograms. The Max time, Min time, and Avg time statistics give you useful statistics for the event you defined no matter what ranges you’ve set up (item 1 in the figure below).
SPA is programmable. Refer to the HP 1660C/CS/CP-Series Logic Analyzers Programmer’s Guide for SPA commands. The Programmer’s Guide is available as an option with the logic analyzer. Contact your HP Sales Office for more information. Changing between SPA and a State/Timing Analyzer If you have configured a state or timing analyzer in the logic analyzer, you can quickly change to SPA, or from SPA to a state or timing analyzer.
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Concepts Understanding how the analyzer does its job will help you use it more effectively and minimize measurement problems. This chapter explains the structure of the file system, the details of transitional timing mode, the general operation of the trigger sequence, and the details of the hardware.
The File System The HP 1660CP-series logic analyzers have a complex internal file system. Many of the file attributes are only accessible over a LAN connection. From the logic analyzer’s front panel, the only parts of the file system you can examine are the hard disk drive and the flexible disk drive.
The File System Directories Directories Hard disk drive When you receive the logic analyzer, the hard disk drive is already DOS-formatted. The factory also creates a directory on the hard disk drive named "/SYSTEM". The /SYSTEM directory is intended to store system software such as backup copies of the operating system files and the performance verification files.
File types File types There are six common file types on the HP 1660CP-series logic analyzer. In addition, there are six common filename endings. The X Window font files and the example files in the /SYSTEM directory do not use these file types.
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The File System File types Filename endings Filename endings are not restricted to certain types. These descriptions are just general guidelines. In addition, other tools you use with the logic analyzer will likely have their own set of filename endings. [none] Of the common file types you can create using the logic analyzer, only the ASCII listings do not have a default ending.
Transitional Mode Theory In Transitional acquisition mode, the timing analyzer samples data at regular intervals, but only stores data when there is a transition between logic levels on currently assigned bits of a pod pair. Each time a level transition occurs on any of the bits, all bits of the pod pair are stored.
Transitional Mode Theory 250-MHz Transitional mode or because transitions take one sample space, 1024 transitions are stored. Subtract 1 for the starting point and you have a minimum of 1023 stored transitions. Storing Time Tags and Transitions Maximum transitions stored If transitions occur at a fast rate, such that there is a transition at each sample point, only one sample is stored for each transition as shown by time tags 17 through 21 above.
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Transitional Mode Theory 250-MHz Transitional mode This operation keeps the pipeline frequency at 125 MHz, which means the transition detector still looks at a full 34 bits. Essentially, the transition detector is looking at two samples at a time instead of one. In the 250-MHz mode, between 682 and 4094 transitions are stored.
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Transitional Mode Theory 250-MHz Transitional mode probability of a transition falling between a sample pair or falling within a sample pair. Maximum transitions stored The following example shows the case where the transitions are occurring at a 4-ns rate: Maximum Transitions Stored In this case, transitions are being detected with each sample so all samples are stored.
Transitional Mode Theory Other transitional timing considerations Other transitional timing considerations Pod pairs are independent In single run mode, each pod pair runs independently. This means when one pod pair fills its trace buffer it will not shut the others down. If you have a pod pair with enabled data lines and no transitions on its lines, you get a message "Storing transitions after trigger for pods nn/nn."...
The Trigger Sequence HP 1660CP-series logic analyzers have triggering and data storage features that allow you to capture only the system activity of interest. Understanding how these features work will help you set up analyzer trigger specifications that satisfy your measurement needs.
The Trigger Sequence Trigger sequence specification Trigger sequence specification See the following figure, which shows a sequence specification with four levels. To define the trigger sequence, you specify sequence-advance, sequence-else, storage, and trigger-on specifications. Each level except the last has two branch conditions, the sequence-advance and sequence-else specification.
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The Trigger Sequence Trigger sequence specification Sequence-else specification The sequence-else branch, sometimes called the "else if" branch or secondary branch, may branch to any other state, including the current state, a previous state, or a later state. The sequence-else specification looks like the following: Else on "<TERM>"...
The Trigger Sequence Analyzer resources Analyzer resources The sequence-advance, sequence-else, storage, and trigger-on specifications are set by a combination of a maximum of 10 pattern terms, 2 range terms, 2 timers, and 2 edge terms (for the timing analyzer only). A resource can only be assigned to one analyzer at a time.
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The Trigger Sequence Analyzer resources Limitations affecting use of analyzer resources There are limitations on the way resources can be combined to form complex pattern expressions. Resources are combined in a four-level hierarchy. First, resources are divided into two groups. The groups can be combined with AND or OR.
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The Trigger Sequence Analyzer resources For example, the following combinations are valid combinations for the analyzer: • (a+b) (In_Range2 + Timer2 > 400 ns) • Out_Range1) + (f xor g) The following combinations are not valid, because resources cross pair boundaries: a xor c •...
The Trigger Sequence Timing analyzer Timing analyzer When you configure a timing analyzer, the trigger sequence follows the general outlines given previously. The trigger sequence of the timing analyzer differs from the state analyzer in the following ways: • There are 10 levels available to build a trigger. •...
To help you move configuration files from one analyzer to another, most HP logic analyzers support automatic translation of analyzer configurations. The HP 1660CP-series logic analyzer can translate configuration files from the following common analyzer models: •...
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The onscreen messages given by the translator will help you identify which analyzer pods must be swapped. If you are using an HP preprocessor, the Preprocessor User’s Guide may contain information showing the cable connections for different analyzer models.
The Analyzer Hardware This section describes the theory of operation for the logic analyzer and describes the self-tests. The information in this section is to help you understand how the logic analyzer operates and what the self-tests are testing. This information is not intended for component-level repair.
The Analyzer Hardware HP 1660CP-series analyzer theory HP 1660CP-series analyzer theory HP 1660CP-Series Logic Analyzer 10-22...
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The Analyzer Hardware HP 1660CP-series analyzer theory CPU board The microprocessor is a Motorola 68EC020 running at 25 MHz. The microprocessor controls all of the functions of the logic analyzer including processing and storing data, displaying data, and configuring the acquisition ICs to obtain and store data.
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HP-IB data to the controller. The controller then buffers the 8-bit HP-IB data bits and generates the bus handshaking signals. The data and handshaking signals are then routed to the HP-IB bus through the octal line drivers/receivers. The drivers/receivers provide data and control signal transfer between the bus and controller.
The Analyzer Hardware Logic acquisition board theory Logic acquisition board theory Logic Acquisition Board Probing The probing circuit includes the probe cable and terminations. The probe cable consists of two 17-channel pods which are connected to the circuit board using a high-density connector. Sixteen single-ended data channels and one single-ended clock/data channel per pod are passed to the circuit board.
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(HP 1660CP), six (HP 1661CP), four (HP 1662CP), or two (HP 1663CP) clock/data channels are available as data channels; however, only six clock/data channels can be assigned as clock channels in the HP 1660CP and HP 1661CP. All clock data channels available in the HP 1662CP and HP 1663CP can be assigned as clock channels.
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The Analyzer Hardware Logic acquisition board theory In addition to the storage qualification and counting functions, the acquisition ASICs also perform master clocking functions. All six state acquisition clocks are fed to each IC, and the ICs generate their own sample clocks. Every time you select RUN, the ICs individually perform a clock optimization before data is stored.
The Analyzer Hardware Pattern Generator board theory Pattern Generator board theory Pattern Generator Board Loop Register The loop register holds the programmable vector flow information. When the module reaches the end of the vector listing, the loop register is queried for the RAM address location of the next user-programmed vector.
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CPU Interface The CPU interface is a single programmable-logic device which interprets the HP 1660CP Logic Analysis System backplane logic and translates the logic into signals to drive and program the pattern generator module. The Clock or Data Pod converts the differential output ECL signal to the logic levels of interest.
The self-tests identify the correct operation of major functional areas in the logic analyzer. The self-tests are not intended for component-level diagnostics. Three types of tests are performed on the HP 1660CP-series logic analyzers: the power-up self-tests, the functional performance verification self-tests, and the parametric performance verification tests.
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Troubleshooting Occasionally, a measurement may not give the expected results. If you encounter difficulties while making measurements, use this chapter to guide you through some possible solutions. Each heading lists a problem you may encounter, along with some possible solutions. Error messages which may appear on the logic analyzer are listed below in quotes "...
Analyzer Problems This section lists general problems that you might encounter while using the analyzer. Intermittent data errors This problem is usually caused by poor connections, incorrect signal levels, or marginal timing. With the logic analyzer and all connected equipment turned off, remove and reseat all cables and probes;...
Analyzer Problems No activity on activity indicators trigger occurs, set the trigger to the module entry address plus 08 hex. (This assumes that there is no immediate data in the instruction stream.) No activity on activity indicators Ensure that the Threshold settings in the Format menu match the logic family being probed.
Preprocessor Problems This section lists problems that you might encounter when using a preprocessor. If the solutions suggested here do not correct the problem, you may have a defective preprocessor. Refer to the User’s Guide for your preprocessor for test procedures. Contact your local Hewlett-Packard Sales Office if you need further assistance.
If +5 V is not present, check the internal preprocessor fuse or current limiting circuit on the logic analyzer. For information on checking this fuse or circuit, refer to the HP 1660C/CS/CP Logic Analyzers Service Guide. • If +5 V is present and the cable connection to the preprocessor appears sound, contact your nearest Hewlett-Packard Sales Office for information on servicing the board.
Preprocessor Problems Erratic trace measurements Erratic trace measurements There are several general problems that can cause erratic variations in trace lists and inverse assembly failures. Ensure that the preprocessor configuration switches are correctly set for the measurement you are trying to make. Some preprocessors include configuration switches for various features (for example, to allow dequeueing of the trace list).
Inverse Assembler Problems This section lists problems that you might encounter while using the inverse assembler. When you obtain incorrect inverse assembly results, it may be unclear whether the problem is in the preprocessor or in your target system. If you follow the suggestions in this section to ensure that you are using the preprocessor and inverse assembler correctly, you can proceed with confidence in debugging your target system.
Inverse Assembler Problems Inverse assembler will not load or run require you to connect cable 5 to analyzer pod 2. See the User’s Guide for your preprocessor for further information. Check the activity indicators for status lines locked in a high or low state.
Error Messages This section lists some of the messages that the analyzer displays when it encounters a problem. ". . . Inverse Assembler Not Found" This error occurs if you rename or delete the inverse assembler file that is attached to the configuration file. Ensure that the inverse assembler file is not renamed or deleted, and that it is on the same flexible disk or in the same directory as the configuration file.
Error Messages "Slow or Missing Clock" "Slow or Missing Clock" This error might occur if the target system is not running properly. Ensure that the target system is on and operating properly. Check your State clock configuration. The proper clocking scheme should be listed in your preprocessor interface User’s Guide.
Error Messages "Must have at least 1 edge specified" "Must have at least 1 edge specified" You must assign at least one clock edge to one of the available clocks in the clocking arrangment. The analyzer will not let you close the clock assignment pop-up until an edge is specified.
Error Messages "Timer is off in sequence level n where it is used" "Timer is off in sequence level n where it is used" If you use timers as part of your trigger sequence, you must remember to turn them on using Timer Control in the Sequence Level pop-up menu. Check that your timers are turned on.
The logic analyzer failed its internal hardware calibration. Run the Performance Verification tests. See Also Chapter 13, "Operator’s Service," or the HP 1660C/CS/CP-Series Logic Analyzers Service Guide for information on running the Performance Verification test. "Warning: Run HALTED due to variable change"...
HP 1660CP-series logic analyzers. Accessories The following accessories are supplied with the HP 1660CP-series logic analyzers. The part numbers are current as of this edition of the User’s Guide, but future upgrades may change the part numbers. Do not be concerned if the accessories you receive have different part numbers.
Specifications (logic analyzer) Specifications (logic analyzer) The specifications are the performance standards against which the product is tested. Refer to the HP 1660C/CS/CP Logic Analyzers Service Guide (available from your HP Sales Office) for testing procedures. Maximum state speed 100 MHz Minimum state clock pulse width 3.5 ns...
125 MHz 250 MHz Maximum timing with glitch rate 125 MHz Memory depth Channel count: HP 1660CP HP 1661CP HP 1662CP HP 1663CP * For all modes except glitch. Characteristics (pattern generator) These characteristics are not specifications, but are included as additional information.
Specifications Supplemental characteristics (logic analyzer) Logic levels TTL, 3-state, TTL/3.3v, 3-state TTL/CMOS, ECL terminated, ECL Unterminated, and differential ECL (without POD) Data inputs 3-bit pattern - level sensing (clock pod) Clock outputs Synchronized to output data Clock input DC to 200 MHz Internal clock period Programmable from 5 ns to 250 us in a 1, 2, 2.5, 4, 5, 8 sequence...
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Timing sequence levels Maximum occurrence counter value 1,048,575 Pattern recognizers Maximum pattern width 136 channels in HP 1660CP, 102 channels in HP 1661CP, 68 channels in HP 1662CP, 34 channels in HP 1663CP Range recognizers Range width 32 bits each...
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Specifications Supplemental characteristics (logic analyzer) Measurement and display functions Displayed waveforms 24 lines maximum, with scrolling across 96 waveforms. Measurement functions Run/Stop functions Run starts acquisition of data in specified trace mode. Stop In single trace mode or the first run of a repetitive acquisition, Stop halts acquisition and displays the current acquisition data.
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Bases Binary, octal, decimal, hexadecimal, ASCII (display only), two’s complement, and user-defined symbols. Symbols 1,000 maximum. Symbols can be downloaded over RS-232 or HP-IB, or the optional LAN. Marker functions Time interval The X and O markers measure the time interval between...
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Specifications Supplemental characteristics (logic analyzer) Altitude To 3067 m (10,000 ft). Vibration Operating: Random vibration 5 to 500 Hz, 10 minutes per axis, ≈0.3 g (rms). Non-operating: Random vibration 5 to 500 Hz, 10 minutes per axis, ≈ 2.41 g (rms); and swept sine resonant search, 5 to 500 Hz, 0.75 g (0-peak), 5 minute resonant dwell at 4 resonances per axis.
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The HP 1660C/CS/CP-Series Logic Analyzers Service Guide contains detailed service procedures. Service guides can be ordered through your HP Sales Office; they are not shipped with the logic analyzer. 13-2...
Preparing For Use This section gives you instructions for preparing the logic analyzer for use. Power requirements The logic analyzer requires a power source of either 115 VAC or 230 VAC, –22 % to +10 %, single phase, 48 to 66 Hz, 200 Watts maximum power.
Preparing For Use To inspect the logic analyzer To inspect the logic analyzer Inspect the shipping container for damage. If the shipping container or cushioning material is damaged, keep them until you have checked the contents of the shipment and checked the instrument mechanically and electrically.
To set the line voltage To set the line voltage When shipped from HP, the line voltage selector is set and an appropriate fuse is installed for operating the instrument in the country of destination. Electrostatic discharge can damage electronic components. Use grounded C A U T I O N wrist straps and mats when performing any service to the logic analyzer.
To test the logic analyzer • If you require a test to verify the specifications, the HP 1660C/CS/CP Series Logic Analyzers Service Guide is required. • If you require a test to initially accept the operation, perform the self-tests described in Troubleshooting in this chapter.
Troubleshooting This section helps you troubleshoot the logic analyzer to find the problem. The troubleshooting consists of flowcharts, self-test instructions, and tests. If you suspect a problem, start at the top of the first flowchart. During the troubleshooting instructions, the flowcharts will direct you to perform other tests.
Troubleshooting To use the flowcharts To use the flowcharts Flowcharts are the primary tool used to isolate problems in the logic analyzer. The flowcharts refer to other tests to help isolate the trouble. The circled letters on the charts indicate connections with the other flowcharts. Start your troubleshooting at the top of the first flowchart.
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Troubleshooting To use the flowcharts Troubleshooting Flowchart 2 13-9...
Troubleshooting To check the power-up tests To check the power-up tests The logic analyzer automatically performs power-up tests when you apply power to the instrument. The revision number of the operating system shows in the upper-right corner of the screen during these power-up tests. As each test completes, either "passed"...
Troubleshooting To run the self-tests To run the self-tests Self-tests identify the correct operation of major functional areas of the analyzer. You can run all self-tests without accessing the interior of the instrument. If a self-test fails, the troubleshooting flowcharts instruct you to change a part of the analzyer.
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Troubleshooting To run the self-tests Press the System key, then select the field next to Sys PV. Select System Test to access the system tests. Select ROM Test. The ROM Test screen is displayed. You can run all tests at one time by running All System Tests. To see more details about each test, you can run each test individually.
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Troubleshooting To run the self-tests Select Run, then select Single. To run a test continuously, select Repetitive. Select Stop to halt a repetitive test. For a Single run, the test runs one time, and the screen shows the results. 13-13...
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Troubleshooting To run the self-tests To exit the ROM Test, select Done. Note that the status changes to PASSED or FAILED. Install a formatted disk that is not write-protected into the flexible disk drive. Connect an RS-232-C loopback connector onto the RS-232-C port.
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Troubleshooting To run the self-tests Select Sys PV, then select Analy PV in the pop-up menu. Select Chip 2 Tests. You can run all the analyzer tests at one time by selecting All Analyzer Tests. To see more details about each test, you can run each test individually. This example shows how to run Chip 2 Tests.
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Troubleshooting To run the self-tests Select Board Tests, then select Run. When the Board Tests are finished, select Done. Select Data Input Inspection. All lines should show activity. Select Done to exit the Data Input Inspection. To exit the tests, press the System key. Select the field to the right of the Sys PV field.
There should be +5 V after the 1 minute reset time. Equipment Required Equipment Critical Specifications Recommended Model/Part Digital Multimeter 0.1 mV resolution, better HP 3478A than 0.005% accuracy • Using the multimeter, verify the +5 V on pins 1 and 39 of the probe cables. 13-17...
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OMF Symbol Table OMF stands glitch is two or more transitions for Object Module File. The across the logic threshold between HP E2450A Symbol Utility uses the consecutive samples. OMF to produce a table of symbols in the executable. Glossary–1...
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Glossary storage qualification Storage READ and term "b" could be I/O qualification allows you to specify WRITE, and the trigger/storage the type of information to be stored macro could be to start storing at in memory. Use storage qualification term "a" and stop storing at term "b." to prevent memory from being filled with unwanted activity.
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A table con- taining the symbols that are created by the user, using the Symbols op- tion in the Format menu. This is the standard symbol capability of the HP logic analyzer. See also OMF Symbol Table. waveform An oscilloscope-like dis- play of a trace.
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Index Branches Taken Stored/Not Stored, 4-15, Compare menu, 3-17, 8-67 to 8-70 $ indicator, 8-54 8-56 bit editing field, 8-70 (<) field less than, 8-50 Branching, 8-49, 8-56 compare full/compare partial field, 8-69 (>) field greater than, 8-50 using, 8-51 copy trace to compare field, 8-69 Break down/restore macros, 8-44 difference listing field, 8-68...
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8-26 operations, 7-3, 8-21 Flexible disk, 7-7 settings, 8-26 Disk operations Flexible disk drive, 7-3, 8-21, 10-4 HP-IB printer autoload, 8-21, 8-23 operations, 7-3 Listen Always, 2-5 copy, 8-21 set up, 2-5 to 2-6 Flowcharts, 13-8 to 13-9...
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Index incorrect inverse assembly, 11-8 inverse assembler will not load or run, Macro 0 field, macro menu, 5-34 no state, 6-4, 10-14 11-9 Macros, 5-11 to 5-13 not, 10-14 no inverse assembly, 11-8 state, 8-47 to 8-48 Number of samples per range, 9-13 timing, 8-45 to 8-46 using, 4-9 main sequence, 5-7...
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Power requirements, 1-3, 13-3 Problems, 11-2 timing analyzers, 4-17 Power-up Tests, 13-10 Programming Sampling methods Preparation for use, 13-3 to 13-6 See HP 1660C/CS Logic Analyzers blind time, 9-9 Preprocessor problems, 11-5 Programmers Guide Saving erratic trace measurements, 11-7 Protocol...
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Index selecting, 8-38 data sampling and sorting, 9-10 System Performance Analysis, 9-2 software instruction, reference, 5-31 example, 9-11 definition, 9-4 Specify States field, 9-13 interpreting the Histogram Display, 9-23 operating characteristics, 9-4 Specifying low and high values, 9-22 operating characteristics, 9-4 using with other features, 9-30 Stacks selecting, 9-6...
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Index Timing Acquisition Mode, 8-34 full channel 125MHz mode, 8-34 User-defined Ranges vs. Symbols, 9-13 conventional full Channel, 8-34 half channel 250MHz mode, 8-34 User-defined threshold, 8-10 conventional half channel, 8-34 other considerations, 8-42, 10-11 User-level macro, modify, 8-49 to 8-51 glitch half channel, 8-34 Trigger Using SPA...
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This Hewlett-Packard This is the first edition of the Hewlett-Packard specifically edition and of any changed product has a warranty HP 1660CP-Series Logic disclaims the implied pages to that edition. against defects in material Analyzers User’s Guide warranties or merchantability...
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Colorado Springs, CO 80907 USA declares, that the product Product Name: Logic Analyzer / Pattern Generator Model Number(s): HP 1660CP, HP 1661CP, HP 1662CP and HP 1663CP Product Option(s): conforms to the following Product Specifications: Safety: IEC 1010-1:1990+A1 / EN 61010-1:1993 UL 3111 CSA-C22.2 No.
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Product Regulations Safety IEC 1010-1:1990+A1 / EN 61010-1:1993 UL 3111 CSA-C22.2 No.1010.1:1993 This Product meets the requirement of the European Communities (EC) EMC Directive 89/336/EEC. Emissions EN55011/CISPR 11 (ISM, Group 1, Class A equipment) IEC 555-2 and IEC 555-3 Immunity EN50082-1 Code Notes...